View ST62T03CB6_6518102.PDF datasheet online --- IC-ON-LINE

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october 2009 doc id 4563 rev 5 1/100 st6200c st6201c st6203c 8-bit mcus with a/d converter, two timers, oscillator safeguard & safe reset memories ? 1k or 2k bytes program memory (otp, eprom, fastrom or rom) with read-out protection ? 64 bytes ram clock, reset and supply management ? enhanced reset system ? low voltage detector (lvd) for safe reset ? clock sources: crystal/ceramic resonator or rc network, external clock, backup oscillator (lfao) ? oscillator safeguard (osg) ? 2 power saving modes: wait and stop interrupt management ? 4 interrupt vector s plus nmi and reset ? 9 external interrupt lines (on 2 vectors) 9 i/o ports ? 9 multifunctional bi directional i/o lines ? 4 alternate function lines ? 3 high sink outputs (20ma) 2 timers ? configurable watchdog timer ? 8-bit timer/counter with a 7-bit prescaler analog peripheral ? 8-bit adc with 4 input channels (except on st6203c) instruction set ? 8-bit data manipulation ? 40 basic instructions ? 9 addressing modes ? bit manipulation development tools ? full hardware/software development package device summary (see section 11.5 for ordering information) pdip16 so16 cdip16w ssop16 features st6200c st6201c st6203c program memory - bytes 1k 2k 1k ram - bytes 64 operating supply 3.0v to 6v analog inputs 4 - clock frequency 8mhz max operating temperature -40c to +125c packages pdip16 / so16 / ssop16 1
table of contents 100 2/100 doc id 4563 rev 5 2 st6200c st6201c st6203c . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 memory maps, programming modes and option bytes . . . . . . . . . . . . . . . . . . . . . . 8 3.1 memory and register maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.1.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.1.2 program space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.1.3 readout protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.1.4 data space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.1.5 stack space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.1.6 data rom window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.2 programming modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.2.1 program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.2.2 eprom erasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.3 option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4 central processing unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 6 4.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 6 4.3 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5 clocks, supply and reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.1 clock system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 8 5.1.1 main oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.1.2 oscillator safeguard (osg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.1.3 low frequency auxiliary oscillator (lfao) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.1.4 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.2 low voltage detector (lvd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.3 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.3.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.3.2 reset sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.3.3 reset pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.3.4 watchdog reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.3.5 lvd reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.4 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.5 interrupt rules and priority management . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.6 interrupts and low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.7 non maskable interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.8 peripheral interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.9 external interrupts (i/o ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.9.1 notes on using external interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.10 interrupt handling procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.10.1interrupt response time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
table of contents doc id 4563 rev 5 3/100 3 5.11 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6 power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1 6.2 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.3 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.4 notes related to wait and stop modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.4.1 exit from wait and stop modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.4.2 recommended mcu configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7 i/o ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 7.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.2.1 digital input modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.2.2 analog inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.2.3 output modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.2.4 alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.2.5 instructions not to be used to access po rt data registers (set, res, inc and dec) 38 7.2.6 recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.3 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.4 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.5 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 8 on-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 8.1 watchdog timer (wdg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 8.1.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 8.1.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1 8.1.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 8.1.4 recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 8.1.5 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 8.1.6 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 8.1.7 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 8.2 8-bit timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 8.2.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 8.2.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5 8.2.3 counter/prescaler description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 8.2.4 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 8.2.5 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 8.2.6 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 8.3 a/d converter (adc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 8.3.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 8.3.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 8 8.3.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 8.3.4 recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 8.3.5 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 8.3.6 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 8.3.7 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 9 instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
table of contents 100 4/100 doc id 4563 rev 5 9.1 st6 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 9.2 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 9.3 instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 10 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 10.1 parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 10.1.1minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 10.1.2typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 10.1.3typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 10.1.4loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 10.1.5pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 10.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 10.2.1voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 10.2.2current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 10.2.3thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 10.3 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 10.3.1general operating conditi ons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 10.3.2operating conditions with low voltage detector (lvd) . . . . . . . . . . . . . . . . . . . . . 61 10.4 supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 10.4.1run modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 10.4.2wait modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 10.4.3stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6 10.4.4supply and clock system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 10.4.5on-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 10.5 clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 10.5.1general timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 8 10.5.2external clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 10.5.3crystal and ceramic resonator oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 10.5.4rc oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 10.5.5oscillator safeguard (osg) and low frequenc y auxiliary oscillator (lfao) . . . . . 71 10.6 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 10.6.1ram and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 10.6.2eprom program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 10.7 emc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 10.7.1functional ems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 10.7.2absolute electrical sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 10.7.3esd pin protection strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 10.8 i/o port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 10.8.1general characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 10.8.2output driving current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 10.9 control pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 10.9.1asynchronous reset pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 10.9.2nmi pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 10.10 timer peripheral characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 10.10.1watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 10.10.28-bit timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 10.11 8-bit adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 1
table of contents doc id 4563 rev 5 5/100 11 general information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 11.1 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 11.2 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 11.3 ecopack information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 11.4 package/socket footprint proposal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 11.5 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 11.6 transfer of customer code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 11.6.1fastrom version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 11.6.2rom version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 12 development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 13 st6 application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 14 summary of changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 9 15 to get more information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 1
st6200c st6201c st6203c 6/100 doc id 4563 rev 5 1 introduction the st6200c, 01c and 03c devices are low cost members of the st62xx 8-bit hcmos family of mi - crocontrollers, which is targeted at low to medium complexity applications. all st62xx devices are based on a building block approach: a common core is surrounded by a number of on-chip periph - erals. the st62e01c is the erasable eprom version of the st62t00c, t01 and t03c devices, which may be used during the development phase for the st62t00c, t01 and t03c target devices, as well as the respective st6200c, 01c and 03c rom devices. otp and eprom devices ar e functionally identi - cal. otp devices offer all the advantages of user programmability at low cost, which make them the ideal choice in a wide r ange of applications where frequent code changes, multiple code versions or last minute programmability are required. the rom based versions offer the same function - ality, selecting the options defined in the program - mable option bytes of the otp/eprom versions in the rom option list (see section 11.6 on page 92 ). the st62p00c, p01c and p03c are the f actory a dvanced s ervice t echnique rom (fastrom) versions of st62t00c, t01 and t03c otp devic - es. they offer the same functionality as otp devices, but they do not have to be programmed by the customer (see section 11 on page 86 ). these compact low-cost devices feature a timer comprising an 8-bit counter with a 7-bit program - mable prescaler, an 8-bit a/d converter with 4 an - alog inputs (depending on device, see device summary on page 1) and a digital watchdog tim - er, making them well suited for a wide range of au - tomotive, appliance and i ndustrial applications. for easy reference, all parametric data are located in section 10 on page 58 . figure 1. block diagram nmi interrupts program pc stack level 1 stack level 2 stack level 3 stack level 4 stack level 5 stack level 6 power supply oscillator reset data rom user selectable data ram 64 bytes port a port b timer 8-bit core 8-bit * a/d converter pa1..pa3 (20ma sink) pb0..pb1 v dd v ss oscin oscout reset watchdog : memory timer (1k or 2k bytes) pb3, pb5..pb7 / ain* * depending on device. please refer to i/o port section. v pp 4
st6200c st6201c st6203c doc id 4563 rev 5 7/100 2 pin description figure 2. 16-pin package pinout table 1. device pin description legend / abbreviations for table 1 : * depending on device. please refer to i/o port section. i = input, o = output, s = supply, ipu = input pull-up the input with pull-up configuration (reset state) is valid as long as the user software does not change it. refer to section 7 "i/o ports" on page 36 for more details on the software configuration of the i/o ports. 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 v dd pb5/ain* ain*/pb6 ain*/pb7 reset v pp nmi oscout oscin v ss pb3/ain* pb1 pb0 pa3/20ma sink pa2/20ma sink pa1/20ma sink it2 it1 itx associated interrupt vector * depending on device. please refer to i/o port section. it2 pin n pin name type main function (after reset) alternate function 1 v dd s main power supply 2 oscin i external clock input or resonator oscillator inverter input 3 oscout o resonator oscillator inverter output or resistor input for rc oscillator 4 nmi i non maskable interrupt (falling edge sensitive) 5 v pp must be held at vss for normal operation, if a 12.5v level is applied to the pin during the reset phase, the device enters eprom programming mode. 6 reset i/o top priority non maskable interrupt (active low) 7 pb7/ain* i/o pin b7 (ipu) analog input 8 pb6/ain* i/o pin b6 (ipu) analog input 9 pb5/ain* i/o pin b5 (ipu) analog input 10 pb3/ain* i/o pin b3 (ipu) analog input 11 pb1 i/o pin b1 (ipu) 12 pb0 i/o pin b0 (ipu) 13 pa3/ 20ma sink i/o pin a3 (ipu) 14 pa2/ 20ma sink i/o pin a2 (ipu) 15 pa1/ 20ma sink i/o pin a1 (ipu) 16 v ss s ground
st6200c st6201c st6203c 8/100 doc id 4563 rev 5 3 memory maps, programming modes and option bytes 3.1 memory and register maps 3.1.1 introduction the mcu operates in three separate memory spaces: program space, data space, and stack space. operation in these three memory spaces is described in the fo llowing paragraphs. briefly, program space contains user program code in otp and user vectors; data space con - tains user data in ram and in otp, and stack space accommodates six levels of stack for sub - routine and interrupt service routine nesting. figure 3. memory addressing diagram program space program interrupt & reset vectors accumulator ram x register y register v register w register 000h 03fh 040h 07fh 080h 081h 082h 083h 084h 0c0h 0ffh data space 000h 0ff0h 0fffh memory window data rom reserved hardware control registers 0bfh (see table 2 ) (see figure 4 ) 1
st6200c st6201c st6203c doc id 4563 rev 5 9/100 memory map (cont?d) figure 4. program memory map (*) reserved areas should be filled with 0ffh 0000h 0affh 0b00h 0b9fh reserved * user program memory 1024 bytes 0ba0h 0f9fh 0fa0h 0fefh 0ff0h 0ff7h 0ff8h 0ffbh 0ffch 0ffdh 0ffeh 0fffh reserved * reserved* interrupt vectors nmi vector user reset vector 0000h 07ffh 0800h 087fh reserved * user program memory 1824 bytes 0880h 0f9fh 0fa0h 0fefh 0ff0h 0ff7h 0ff8h 0ffbh 0ffch 0ffdh 0ffeh 0fffh reserved * reserved* interrupt vectors nmi vector user reset vector st62t03c,t00c st62t01c, e01c not implemented not implemented 1
st6200c st6201c st6203c 10/100 doc id 4563 rev 5 memory map (cont?d) 3.1.2 program space program space comprises the instructions to be executed, the data required for immediate ad - dressing mode instructions, the reserved factory test area and the user vectors. program space is addressed via the 12-bit pr ogram counter register (pc register). thus, the mcu is capable of ad - dressing 4k bytes of memory directly. 3.1.3 readout protection the program memory in in otp, eprom or rom devices can be protected against external readout of memory by setting the readout protection bit in the option byte ( section 3.3 on page 15 ). in the eprom parts, readout protection option can be desactivated only by u.v. erasure that also results in the whole eprom context being erased. note: once the readout protection is activated, it is no longer possible, ev en for stmicr oelectronics, to gain access to the otp or rom contents. re - turned parts can therefore not be accepted if the readout protection bit is set. 3.1.4 data space data space accommodates all the data necessary for processing the user pr ogram. this space com - prises the ram resource, the processor core and peripheral registers, as well as read-only data such as constants and look-up tables in otp/ eprom. 3.1.4.1 data rom all read-only data is physica lly stored in program memory, which also accommodates the program space. the program memory consequently con - tains the program code to be executed, as well as the constants and look-up tables required by the application. the data space locations in which the different constants and look-up tables are addressed by the processor core may be thought of as a 64-byte window through which it is possible to access the read-only data stored in otp/eprom. 3.1.4.2 data ram the data space includes the user ram area, the accumulator (a), the indirect registers (x), (y), the short direct registers (v), (w), the i/o port regis - ters, the peripheral data and control registers, the interrupt option register and the data rom win - dow register (drwr register). 3.1.5 stack space stack space consists of six 12-bit registers which are used to stack subroutine and interrupt return addresses, as well as the current program counter contents. 1
st6200c st6201c st6203c doc id 4563 rev 5 11/100 memory map (cont?d) table 2. hardware register map legend : x = undefined, r/w = read/write, ro = read-only bi t(s) in the register, wo = write-only bit(s) in the register. notes : 1. the contents of the i/o port dr registers are r eadable only in output configurat ion. in input configura - tion, the values of the i/o pins are retu rned instead of the dr register contents. 2. the bits associated with unavailable pins must always be kept at their reset value. 3. do not use single-bit instructions (set, res...) on po rt data registers if any pin of the port is configured in input mode (refer to section 7 "i/o ports" on page 36 for more details). 4. depending on device. see device summary on page 1. address block register label register name reset status remarks 080h to 083h cpu x,y,v,w x,y index registers v,w short direct registers xxh r/w 0c0h 0c1h i/o ports dra 1) 2) 3) drb 1) 2) 3) port a data register port b data register 00h 00h r/w r/w 0c2h 0c3h reserved (2 bytes) 0c4h 0c5h i/o ports ddra 2) ddrb 2) port a direction register port b direction register 00h 00h r/w r/w 0c6h 0c7h reserved (2 bytes) 0c8h cpu ior interrupt option register xxh write-only 0c9h rom drwr data rom window register xxh write-only 0cah 0cbh reserved (2 bytes) 0cch 0cdh i/o ports ora 2) orb 2) port a option register port b option register 00h 00h r/w r/w 0ceh 0cfh reserved (2 bytes) 0d0h 0d1h adc adr adcr a/d converter data register a/d converter control register xxh 40h read-only ro/wo 0d2h 0d3h 0d4h timer 1 pscr tcr tscr timer 1 prescaler register timer 1 downcounter register timer 1 status control register 7fh 0ffh 00h r/w r/w r/w 0d5h to 0d7h reserved (3 bytes) 0d8h watchdog timer wdgr watchdog register 0feh r/w 0d9h to 0feh reserved (38 bytes) 0ffh cpu a accumulator xxh r/w 1
st6200c st6201c st6203c 12/100 doc id 4563 rev 5 memory map (cont?d) 3.1.6 data rom window the data read-only memory window is located from address 0040h to address 007fh in data space. it allows direct reading of 64 consecutive bytes located anywhere in program memory, be - tween address 0000h and 0fffh. there are 64 blocks of 64 bytes in a 4k device: ? block 0 is related to the address range 0000h to 003fh. ? block 1 is related to the address range 0040h to 007fh. and so on... all the program memory can therefore be used to store either instructions or read-only data. the data rom window can be moved in steps of 64 bytes along the program me mory by writing the appropriate code in the data rom window regis - ter (drwr). figure 5. data rom window 3.1.6.1 data rom window register (drwr) the drwr can be addressed like any ram loca - tion in the data space. this register is used to select the 64-byte block of program memory to be read in the data rom win - dow (from address 40h to address 7fh in data space). the drwr register is not cleared on re - set, therefore it must be written to before access - ing the data read-only memory window area for the first time. address: 0c9h ? write only reset value = xxh (undefined) bits 7:6 = reserved , must be cleared. bit 5:0 = drwr[5:0] data read-only memory win - dow register bits. these are the data read-only memory window bits that correspond to the upper bits of the data read- only memory space. caution: this register is undefined on reset, it is write-only, therefore do not read it nor access it us - ing read-modify-write in structions (set, res, inc and dec). 0000h 0fffh 000h 040h 07fh 0ffh data rom window data space 64-byte rom program space 7 0 - - drwr5 drwr4 drwr3 drwr2 drwr1 drwr0 1
st6200c st6201c st6203c doc id 4563 rev 5 13/100 memory map (cont?d) 3.1.6.2 data rom window memory addressing in cases where some data (look-up tables for ex - ample) are stored in program memory, reading these data requires the use of the data rom win - dow mechanism. to do this: 1. the drwr register has to be loaded with the 64-byte block number where the data are located (in program memory). this number also gives the start address of the block. 2. then, the offset address of the byte in the data rom window (corresponding to the offset in the 64-byte block in program memory) has to be load - ed in a register (a, x,...). when the above two steps are completed, the data can be read. to understand how to determine the drwr and the content of the register, please refer to the ex - ample shown in figure 6 . in any case the calcula - tion is automatically handled by the st6 develop - ment tools. please refer to the user manual of the correspod - ing tool. 3.1.6.3 recommendations care is required when handling the drwr regis - ter as it is write only. for this reason, the drwr contents should not be changed while executing an interrupt service routine, as the service routine cannot save and then restore the register?s previ - ous contents. if it is impos sible to avoid writing to the drwr during the interrupt service routine, an image of the register must be saved in a ram lo - cation, and each time the program writes to the drwr, it must also write to the image register. the image register must be written first so that, if an interrupt occurs between the two instructions, the drwr is not affected. figure 6. data rom window memory addressing data program space data space 0000h 0400h 0421h 07ffh 64 bytes offset 000h 040h 061h 07fh offset 21h 0ffh drwr data address in program memory : 421h drwr content : 421h / 3fh (64) = 10h data is located in 64-bytes window number 10h 64-byte window start address : 10h x 3fh = 400h register (a, x,...)content : offset = (421h - 400h) + 40h ( data rom window start address in data space) = 61h 10h data 1
st6200c st6201c st6203c 14/100 doc id 4563 rev 5 3.2 programming modes 3.2.1 program memory eprom/otp programming mode is set by a +12.5v voltage applied to the test/v pp pin. the programming flow of the st62t00c, t01/e01c and t03c is described in the user manual of the eprom programming board. table 3. st6200c/03c program memory map table 4. st6201c program memory map note : otp/eprom devices can be programmed with the development tools available from stmicroelectronics (please refer to section 12 on page 95 ). 3.2.2 eprom erasing the eprom devices can be erased by exposure to ultra violet light. the characteristics of the mcu are such that erasure begins when the memory is exposed to light with a wa ve lengths shorter than approximately 4000?. it should be noted that sun - light and some types of fluorescent lamps have wavelengths in the range 3000-4000?. it is thus recommended that the window of the mcu packages be covered by an opaque label to prevent unintentional erasure problems when test - ing the application in such an environment. the recommended erasure pr ocedure is exposure to short wave ultraviolet light which have a wave- length 2537?. the integrated dose (i.e. u.v. inten - sity x exposure time) fo r erasure should be a mini - mum of 30w-sec/cm 2 . the erasure time with this dosage is approximately 30 to 40 minutes using an ultraviolet lamp with 12000w/cm 2 power rating. the eprom device should be placed within 2.5cm (1inch) of the lamp tubes during erasure. device address description 0000h-0b9fh 0ba0h-0f9fh 0fa0h-0fefh 0ff0h-0ff7h 0ff8h-0ffbh 0ffch-0ffdh 0ffeh-0fffh reserved user rom reserved interrupt vectors reserved nmi interrupt vector reset vector device address description 0000h-087fh 0880h-0f9fh 0fa0h-0fefh 0ff0h-0ff7h 0ff8h-0ffbh 0ffch-0ffdh 0ffeh-0fffh reserved user rom reserved interrupt vectors reserved nmi interrupt vector reset vector 1
st6200c st6201c st6203c doc id 4563 rev 5 15/100 3.3 option bytes each device is available for production in user pro - grammable versions (otp) as well as in factory coded versions (rom). otp devices are shipped to customers with a default content (00h), while rom factory coded parts contain the code sup - plied by the customer. this implies that otp de - vices have to be configured by the customer using the option bytes while the rom devices are facto - ry-configured. the two option bytes allow the hardware configu - ration of the microcontroller to be selected. the option bytes have no address in the memory map and can be accessed only in programming mode (for example using a standard st6 program - ming tool). in masked rom devices, the option bytes are fixed in hardware by the rom code (see section 11.6.2 "rom version" on page 93 ). it is there - fore impossible to read the option bytes. the option bytes can be only programmed once. it is not possible to change the selected options after they have been programmed. in order to reach the pow er consumption value in - dicated in section 10.4 , the option byte must be programmed to its default value. otherwise, an over-consumpti on will occur. msb option byte bits 15:11 = reserved , must be always cleared. bit 10 = reserved , must be always set. bit 9 = extcntl external stop mode control . 0: extcntl mode not available. stop mode is not available with the watchdog active. 1: extcntl mode available. stop mode is avail - able with the watchdog active by setting nmi pin to one. bit 8 = lvd low voltage detector on/off . this option bit enable or disable the low voltage detector (lvd) feature. 0: low voltage detector disabled 1: low voltage detector enabled . lsb option byte bit 7 = protect readout protection. this option bit enables or di sables external access to the internal program memory. 0: program memory not read-out protected 1: program memory read-out protected bit 6 = osc oscillator selection . this option bit selects the main oscillator type. 0: quartz crystal, cerami c resonator or external clock 1: rc network bit 5 = reserved , must be always cleared. bit 4 = reserved , must be always set. bit 3 = nmi pull nmi pull-up on/off. this option bit enables or di sables the internal pull- up on the nmi pin. 0: pull-up disabled 1: pull-up enabled bit 2 = reserved , must be always set. bit 1 = wdact hardware or software watchdog. this option bit selects the watchdog type. 0: software (watchdog to be enabled by software) 1: hardware (watchdog always enabled) bit 0 = osgen oscillator safeguard on/off. this option bit enables or disables the oscillator safeguard (osg) feature. 0: oscillator safeguard disabled 1: oscillator safeguard enabled msb option byte 15 8 lsb option byte 7 0 reserved ext ctl lvd pro - tect osc res. res. nmi pull res. wd act osg en default value x x x x x x x x x x x x x x x x 1
st6200c st6201c st6203c 16/100 doc id 4563 rev 5 4 central processing unit 4.1 introduction the cpu core of st6 devices is independent of the i/o or memory configuration. as such, it may be thought of as an independent central processor communicating with on-chip i/o, memory and pe - ripherals via internal address, data, and control buses. 4.2 main features 40 basic instructions 9 main addressing modes two 8-bit index registers two 8-bit short direct registers low power modes maskable hardware interrupts 6-level hardware stack 4.3 cpu registers the st6 family cpu core features six registers and three pairs of flags avai lable to the programmer. these are described in the following paragraphs. accumulator (a) . the accumulator is an 8-bit general purpose register used in all arithmetic cal - culations, logical operations, and data manipula - tions. the accumulator can be addressed in data space as a ram location at address ffh. thus the st6 can manipulate the accumulator just like any other register in data space. index registers (x, y). these two r egisters are used in indirect addressing mode as pointers to memory locations in data space. they can also be accessed in direct, short direct, or bit direct addressing modes. they are mapped in data space at addresses 80h (x) and 81h (y) and can be accessed like any other memory location. short direct registers (v, w). these two regis - ters are used in short direct addressing mode. this means that the data stored in v or w can be accessed with a one-byte instruction (four cpu cy - cles). v and w can also be accessed using direct and bit direct addressing modes. they are mapped in data space at addresses 82h (v) and 83h (w) and can be accessed like any other mem - ory location. note : the x and y registers can also be used as short direct registers in the same way as v and w. program counter (pc) . the program counter is a 12-bit register which cont ains the address of the next instruction to be executed by the core. this rom location may be an opcode, an operand, or the address of an operand. figure 7. cpu registers accumulator x index register y index register program counter reset value = reset vector @ 0ffeh-0fffh 70 70 70 0 11 reset value = xxh reset value = xxh reset value = xxh x = undefined value v short indirect 70 reset value = xxh w short indirect 70 reset value = xxh normal flags cn zn ci zi cnmi znmi interrupt flags nmi flags six level stack register register 1
st6200c st6201c st6203c doc id 4563 rev 5 17/100 cpu registers (cont?d) the 12-bit length allows the direct addressing of 4096 bytes in program space. however, if the program space contains more than 4096 bytes, the additional memory in program space can be addressed by using the program rom page register. the pc value is incremented after reading the ad - dress of the current instruction. to execute relative jumps, the pc and the offset are shifted through the alu, where they are added; the result is then shifted back into the pc. the program counter can be changed in the following ways: ? jp (jump) instruction pc = jump address ? call instruction pc = call address ? relative branch instructionpc = pc +/- offset ? interrupt pc = interrupt vector ? reset pc = reset vector ? ret & reti instructions pc = pop (stack) ? normal instruction pc = pc + 1 flags (c, z) . the st6 cpu includes three pairs of flags (carry and zero), each pair being associated with one of the three normal modes of operation: normal mode, interrupt mode and non maskable interrupt mode. each pair consists of a carry flag and a zero flag. one pair (cn, zn) is used during normal operation, another pair is used dur - ing interrupt mode (ci, zi), and a third pair is used in the non maskable interrupt mode (cnmi, zn - mi). the st6 cpu uses the pair of flags associated with the current mode: as soon as an interrupt (or a non maskable interrupt) is generated, the st6 cpu uses the interrupt fl ags (or the nmi flags) in - stead of the normal flags. when the reti instruc - tion is executed, the previ ously used set of flags is restored. it should be noted that each flag set can only be addressed in its own context (non maska - ble interrupt, normal interrupt or main routine). the flags are not cleared during context switching and thus retain their status. c : carry flag. this bit is set when a carry or a borrow occurs dur - ing arithmetic operations; otherwise it is cleared. the carry flag is also set to the value of the bit tested in a bit test instruction; it also participates in the rotate left instruction. 0: no carry has occured 1: a carry has occured z : zero flag this flag is set if the result of the last arithmetic or logical operation was equal to zero; otherwise it is cleared. 0: the result of the last operation is different from zero 1: the result of the last operation is zero switching between the three sets of flags is per - formed automatically when an nmi, an interrupt or a reti instruction occurs. as nmi mode is auto - matically selected after the reset of the mcu, the st6 core uses the nmi flags first. stack. the st6 cpu includes a true lifo (last in first out) hardware stack which eliminates the need for a stack pointer. the stack consists of six separate 12-bit ram locations that do not belong to the data space ram area. when a subroutine call (or interrupt request) occurs, the contents of each level are shifted into the next level down, while the content of the pc is shifted into the first level (the original contents of the sixth stack level are lost). when a subroutine or interrupt return oc - curs (ret or reti instructions), the first level reg - ister is shifted back into the pc and the value of each level is popped back into the previous level. figure 8. stack manipulation since the accumulator, in common with all other data space registers, is not stored in this stack, management of these registers should be per - formed within the subroutine. caution: the stack will remain in its ?deepest? po - sition if more than 6 nest ed calls or interrupts are executed, and consequently the last return ad - dress will be lost. it will also remain in its highest position if the stack is empty and a ret or reti is executed. in this case the next instruction will be executed. level 1 level 2 level 3 level 4 level 5 level 6 on interrupt, or subroutine call on return from interrupt, or subroutine program counter 1
st6200c st6201c st6203c 18/100 doc id 4563 rev 5 5 clocks, supply and reset 5.1 clock system the main oscillator of the mcu can be driven by any of these clock sources: ? external clock signal ? external at-cut parallel-resonant crystal ? external ceramic resonator ? external rc network (r net ). in addition, an on-chip low frequency auxiliary oscillator (lfao) is ava ilable as a back-up clock system or to reduce power consumption. an optional oscillator safeguard (osg) filters spikes from the oscillator lines, and switches to the lfao backup oscillator in the event of main oscil - lator failure. it also automatically limits the internal clock frequency (f int ) as a function of v dd , in order to guarantee correct operation. these functions are illustrated in figure 10 , and figure 11 . table 5 illustrates various possible oscillator con - figurations using an extern al crystal or ceramic resonator, an external clock input, an external re - sistor (r net ), or the lowest cost solution using only the lfao. for more details on configuring the clock options, refer to the option bytes section of this document. the internal mcu clock frequency (f int ) is divided by 12 to drive the timer, the watchdog timer and the a/d converter, by 13 to drive the cpu core and the spi and by 1 or 3 to drive the artimer, as shown in figure 9 . with an 8 mhz oscillator, the fastest cpu cycle is therefore 1.625s. a cpu cycle is the smallest unit of time needed to execute any operation (for instance, to increment the program counter). an instruction may require two, four, or five cp u cycles for execution. figure 9. clock circuit block diagram main oscillator osg lfao core : 13 : 12 8-bit timer watchdog f int oscoff bit adc 0 1 filtering oscillator safeguard (osg) osg enable option bit (see option byte section) (adcr register) f osc * depending on device. see device summary on page 1. * * oscillator divider spi : 1 : 3 8-bit artimer 8-bit artimer 1
st6200c st6201c st6203c doc id 4563 rev 5 19/100 clock system (cont?d) 5.1.1 main oscillator the oscillator configuration is specified by select - ing the appropriate option in the option bytes (refer to the option bytes section of this document). when the crystal/resonator option is se - lected, it must be used with a quartz crystal, a ce - ramic resonator or an external signal provided on the oscin pin. when the rc network option is selected, the system clock is generated by an ex - ternal resistor (the capacitor is implemented inter - nally). the main oscillator can be turned off (when the osg enabled option is selected) by setting the oscoff bit of the adc control register (not available on some devices). this will aut omatically start the low frequency au xiliary oscillator (lfao). the main oscillator can be turned off by resetting the oscoff bit of the a/d converter control reg - ister or by resetting the mcu. when the main os - cillator starts there is a delay made up of the oscil - lator start-up delay period plus the duration of the software instruction at a clock frequency f lfao . caution: it should be noted that when the rc net - work option is selected, the accuracy of the fre - quency is about 20% so it may not be suitable for some applications (for more details, please refer to the electrical char acteristics section). table 5. oscillator configurations notes: 1. to select the options shown in column 1 of the above table, refer to the option byte section. 2.this schematic are given for guidance only and are sub - ject to the schematics given by the crystal or ceramic res - onator manufacturer. 3. for more details, please refer to the electrical charac - teristics section. hardware configuration crystal/resonator option 1) crystal/resonator option 1) rc network option 1) osg enabled option 1) oscin oscout external st6 clock nc external clock oscin oscout load capacitors 3) st6 c l2 c l1 crystal/resonator clock 2) oscin oscout st6 r net nc rc network oscin oscout st6 lfao nc 1
st6200c st6201c st6203c 20/100 doc id 4563 rev 5 clock system (cont?d) 5.1.2 oscillator safeguard (osg) the oscillator safeguar d (osg) feature is a means of dramatically improving the operational integrity of the mcu. it is available when the osg enabled option is selected in the option byte (re - fer to the option bytes section of this document). the osg acts as a filter whose cross-over fre - quency is device dependent and provides three basic functions: ? filtering spikes on the oscillator lines which would result in driving the cpu at excessive fre - quencies ? management of the low frequency auxiliary oscillator (lfao), (useabl e as low cost internal clock source, backup clock in case of main oscil - lator failure or for lo w power consumption) ? automatically limiting the f int clock frequency as a function of supply voltage, to ensure correct operation even if the power supply drops. 5.1.2.1 spike filtering spikes on the oscillator lines result in an effectively increased internal clock frequency. in the absence of an osg circuit, this may lead to an over fre - quency for a given power supply voltage. the osg filters out such spikes (as illustrated in figure 10 ). in all cases, when the osg is active, the max - imum internal clock frequency, f int , is limited to f osg , which is supply voltage dependent. 5.1.2.2 management of supply voltage variations over-frequency, at a given power supply level, is seen by the osg as spikes; it therefore filters out some cycles in order that the internal clock fre - quency of the device is kept within the range the particular device can stand (depending on v dd ), and below f osg : the maximum authorised frequen - cy with osg enabled. 5.1.2.3 lfao management when the osg is enabled, the low frequency auxiliary oscillat or can be used (see section 5.1.3 ). note: the osg should be used wherever possible as it provides maximum security for the applica - tion. it should be noted however, that it can in - crease power consumption and reduce the maxi - mum operating frequency to f osg (see electrical characteristics section). caution: care has to be taken when using the osg, as the internal frequency is defined between a minimum and a maximum value and may vary depending on both v dd and temperature. for pre - cise timing measurements, it is not recommended to use the osg. figure 10. osg filtering function figure 11. lfao oscillator function f osc f osg f int f osc< f osg f osc> f osg main oscillator stops main oscillator restarts internal clock driven by lfao f osc f int f lfao 1
st6200c st6201c st6203c doc id 4563 rev 5 21/100 clock system (cont?d) 5.1.3 low frequency auxiliary oscillator (lfao) the low frequency auxiliar y oscillator has three main purposes. firstly, it can be used to reduce power consumption in non timing critical routines. secondly, it offers a fully integrated system clock, without any external components. lastly, it acts as a backup oscillator in case of main oscillator fail - ure. this oscillator is available when the osg ena - bled option is selected in the option byte (refer to the option bytes section of this document). in this case, it automatically star ts one of its periods after the first missing edge of t he main oscillator, what - ever the reason for the fa ilure (main oscillator de - fective, no clock circuitry provided, main oscillator switched off...). see figure 11 . user code, normal interrupts, wait and stop in - structions, are processed as normal, at the re - duced f lfao frequency. the a/d converter accura - cy is decreased, since t he internal frequency is be - low 1.2 mhz. at power on, until the main oscillator starts, the re - set delay counter is driven by the lfao. if the main oscillator starts before the 2048 cycle delay has elapsed, it takes over. the low frequency auxiliary oscillator is auto - matically switched off as soon as the main oscilla - tor starts. 5.1.4 register description adc control register (adcr) address: 0d1h ? read/write reset value: 0100 0000 (40h) bit 7:3, 1:0 = adcr[7:3], adcr[1:0] adc control register . these bits are used to cont rol the a/d converter (if available on the device) otherwise they are not used. bit 2 = oscoff main oscillator off. 0: main oscillator enabled 1: main oscillator disabled note: the osg must be enabled using the os - gen option in the option byte, otherwise the os - coff setting has no effect. 7 0 adcr 7 adcr 6 adcr 5 adcr 4 adcr 3 osc off adcr 1 adcr 0 1
st6200c st6201c st6203c 22/100 doc id 4563 rev 5 5.2 low voltage detector (lvd) the on-chip low voltage detector is enabled by setting a bit in the option bytes (refer to the option bytes section of this document). the lvd allows the device to be used without any external reset circuitry. in this case, the reset pin should be left unconnected. if the lvd is not used, an external circuit is manda - tory to ensure correct power on reset operation, see figure in the reset section. for more details, please refer to the application note an669. the lvd generates a static reset when the supply voltage is below a reference value. this means that it secures the power-up as well as the power- down keeping the st6 in reset. the v it- reference value for a voltage drop is lower than the v it+ reference value for power-on in order to avoid a parasitic reset when the mcu starts run - ning and sinks current on the supply (hysteresis). the lvd reset circuitry generates a reset when v dd is below: ? v it+ when v dd is rising ? v it- when v dd is falling the lvd function is illustrated in figure 12 . if the lvd is enabled, the mcu can be in only one of two states: ? over the input threshol d voltage, it is running un - der full software control ? below the input threshold voltage, it is in static safe reset in these conditions, secure operation is guaran - teed without the need for external reset hardware. during a low voltage detector reset, the reset pin is held low, thus permitting the mcu to reset other devices. figure 12. low voltage detector reset v dd v it+ reset v it- v hyst 1
st6200c st6201c st6203c doc id 4563 rev 5 23/100 5.3 reset 5.3.1 introduction the mcu can be reset in three ways: a low pulse input on the reset pin internal watchdog reset internal low voltage detector (lvd) reset 5.3.2 reset sequence the basic reset sequence consists of 3 main phases: internal (watchdog or lvd) or external reset event a delay of 2048 clock (f int ) cycles reset vector fetch the reset delay allows the oscillator to stabilise and ensures that recovery has taken place from the reset state. the reset vector fetch phase duration is 2 clock cycles. when a reset occurs: ? the stack is cleared ? the pc is loaded with the address of the reset vector. it is located in program rom starting at address 0ffeh. a jump to the beginning of the user program must be coded at this address. ? the interrupt flag is automatically set, so that the cpu is in non maskable interrupt mode. this prevents the initialization routine from being in - terrupted. the initialization routine should there - fore be terminated by a reti instruction, in order to go back to normal mode. figure 13. reset sequence v dd reset pin watchdog v it+ v it- watchdog underflow reset 2048 clock cycle (f int ) delay lvd reset internal run reset run run run reset reset reset 1
st6200c st6201c st6203c 24/100 doc id 4563 rev 5 reset (cont?d) 5.3.3 reset pin the reset pin may be connected to a device on the application board in order to reset the mcu if required. the reset pin may be pulled low in run, wait or stop mode. this input can be used to reset the internal state of the mcu and en - sure it starts-up correctl y. the pin, which is con - nected to an internal pull-up, is active low and fea - tures a schmitt trigger input. a delay (2048 clock cycles) added to the exter nal signal ensures that even short pulses on the reset pin are accepted as valid, provided v dd has completed its rising phase and that the oscillator is running correctly (normal run or wait modes). the mcu is kept in the reset state as long as the reset pin is held low. if the reset pin is grounded while the mcu is in run or wait modes, processing of the user pro - gram is stopped (run m ode only), the i/o ports are configured as inputs with pull-up resistors and the main oscillator is restarted. when the level on the reset pin then goes high, the initialization se - quence is executed at the end of the internal delay period. if the reset pin is grounded while the mcu is in stop mode, the oscillator starts up and all the i/o ports are configured as inputs with pull-up resis - tors. when the reset pin level then goes high, the initialization sequence is executed at the end of the internal delay period. a simple external reset circuitry is shown in fig - ure 15 . for more details, please refer to the appli - cation note an669. figure 14. reset block diagram f int counter reset watchdog reset lvd reset internal reset r esd 1) 1) resistive esd protection. v dd r pu 2048 clock cycles 1
st6200c st6201c st6203c doc id 4563 rev 5 25/100 reset (cont?d) 5.3.4 watchdog reset the mcu provides a watchdog timer function in order to be able to recover from software hang- ups. if the watchdog regist er is not refreshed be - fore an end-of-count condition is reached, a watchdog reset is generated. after a watchdog reset, the mcu restarts in the same way as if a reset was generated by the re - set pin. note: when a watchdog reset occurs, the reset pin is tied low for very s hort time period, to flag the reset phase. this time is not long enough to reset external circuits. for more details refer to the watchdog timer chapter. 5.3.5 lvd reset two different reset sequences caused by the in - ternal lvd circuitry can be distinguished: power-on reset voltage drop reset during an lvd reset, the reset pin is pulled low when v dd 4.7 k int latch cleared nmi mask set (if present) select nmi mode flags is reset still present? yes put ffeh on address bus from reset locations ffeh/fffh no fetch instruction load pc internal reset reset 2048 clock cycle delay 1
st6200c st6201c st6203c 26/100 doc id 4563 rev 5 5.4 interrupts the st6 core may be interrupted by four maska - ble interrupt sources, in addition to a non maska - ble interrupt (nmi) source. the interrupt process - ing flowchart is shown in figure 18 . maskable interrupts must be enabled by setting the gen bit in the ior register. however, even if they are disabled (gen bit = 0), interrupt events are latched and may be proc essed as soon as the gen bit is set. each source is associated with a specific interrupt vector, located in program space (see table 7 ). in the vector location, the user must write a jump in - struction to the associated interrupt service rou - tine. when an interrupt source generates an interrupt request, the pc register is loaded with the address of the interrupt vector, which then causes a jump to the relevant interrupt service routine, thus serv - icing the interrupt. interrupt are triggered by events either on external pins, or from the on-ch ip peripherals. several events can be ored on the same interrupt vector. on-chip peripherals have flag registers to deter - mine which event triggered the interrupt. figure 17. interrupts block diagram nmi esb bit v dd latch cleared by h/w at start of vector #0 routine vector #0 les bit 1 0 latch cleared by h/w at start of vector #1 vector #2 vector #3 vector #4 latch cleared by h/w at start of vector #2 routine i/o port register configuration ?input with interrupt? i/o port register configuration ?input with interrupt? exit from stop/wait vector #1 routine timer a/d converter * tmz bit eti bit eai bit eoc bit gen bit pb0..pb1 pa1..pa3 (tscr register) (adcr register) (ior register) (ior register) (ior register) pb3 pb5..pb7 * depending on device. see device summary on page 1. 1
st6200c st6201c st6203c doc id 4563 rev 5 27/100 5.5 interrupt rules and priority management a reset can interrupt the nmi and peripheral interrupt routines the non maskable interrupt request has the highest priority and can interrupt any peripheral interrupt routine at any time but cannot interrupt another nmi interrupt. no peripheral interrupt can interrupt another. if more than one interrupt request is pending, these are processed by the processor core according to their priority level: vector #1 has the highest priority while vector #4 the lowest. the priority of each interrupt source is fixed by hardware (see interrupt mapping table ). 5.6 interrupts and low power modes all interrupts cause the pr ocessor to exit from wait mode. only the external and some specific interrupts from the on-ch ip peripherals cause the processor to exit from stop mode (refer to the ?exit from stop? column in the interrupt mapping table). 5.7 non maskable interrupt this interrupt is triggered when a falling edge oc - curs on the nmi pin regardless of the state of the gen bit in the ior regist er. an interrupt request on nmi vector #0 is latched by a flip flop which is automatically reset by the core at the beginning of the nmi service routine. 5.8 peripheral interrupts different peripheral interrupt flags in the peripheral control registers are able to cause an interrupt when they are active if both: ? the gen bit of the ior register is set ? the corresponding enable bit is set in the periph - eral control register. peripheral interrupts are linked to vectors #3 and #4. interrupt requests are flagged by a bit in their corresponding control regist er. this means that a request cannot be lost, because the flag bit must be cleared by user software. 1
st6200c st6201c st6203c 28/100 doc id 4563 rev 5 5.9 external interrupts (i/o ports) external interrupt vectors can be loaded into the pc register if the corr esponding external interrupt occurred and if the gen bit is set. these interrupts allow the processor to exit from stop mode. the external interrupt polarity is selected through the ior register. external interrupts are linked to vectors #1 and # 2. interrupt requests on vector #1 can be configured either as edge or level-s ensitive using the les bit in the ior register. interrupt requests from vector #2 are always edge sensitive. the edge polarity can be configured us - ing the esb bit in the ior register. in edge-sensitive mode, a latch is set when a edge occurs on the interrupt source line and is cleared when the associated interrupt routine is started. so, an interrupt request can be stored until com - pletion of the currently ex ecuting interrupt routine, before being processed. if several interrupt re - quests occurs before completion of the current in - terrupt routine, only t he first request is stored. storing of interrupt requests is not possible in level sensitive mode. to be taken into account, the low level must be present on the interrupt pin when the mcu samples the line after instruction execution. 5.9.1 notes on using external interrupts esb bit spurious interrupt on vector #2 if a pin associated with interrupt vector #2 is con - figured as interrupt with pull-up, whenever vector #2 is configured to be ri sing edge sensitive (by set - ting the esb bit in the ior register), an interrupt is latched although a rising edge may not have oc - cured on the associated pin. this is due to the vector #2 circuitry.the worka - round is to discard this first interrupt request in the routine (using a flag for example). masking of one interrupt by another on vector #2. when two or more port pins (associated with inter - rupt vector #2) are conf igured together as input with interrupt (falling edge sensitive), as long as one pin is stuck at '0', the other pin can never gen - erate an interrupt even if an active edge occurs at this pin. the same thi ng occurs when one pin is stuck at '1' and interrupt vector #2 is configured as rising edge sensitive. to avoid this the first pi n must input a signal that goes back up to '1' right after the falling edge. oth - erwise, in the interrupt routine for the first pin, de - activate the ?input with interrupt? mode using the port control registers (ddr , or, dr). an active edge on another pin can then be latched. i/o port configuration spurious interrupt on vector #2 if a pin associated with inte rrupt vector #2 is in ?in - put with pull-up? state, a ?0? level is present on the pin and the esb bit = 0, when the i/o pin is config - ured as interrupt with pul l-up by writing to the ddrx, orx and drx register bits, an interrupt is latched although a falling edge may not have oc - curred on the associated pin. in the opposite case, if the pin is in interrupt with pull-up state , a 0 level is present on the pin and the esb bit =1, when the i/o port is configured as input with pull-up by writing to the ddrx, orx and drx bits, an interrupt is latched although a rising edge may not have occurred on the associated pin. 1
st6200c st6201c st6203c doc id 4563 rev 5 29/100 5.10 interrupt handling procedure the interrupt procedure is ve ry similar to a call pro - cedure, in fact the user can consider the interrupt as an asynchronous call pr ocedure. as this is an asynchronous event, the user cannot know the context and the time at which it occurred. as a re - sult, the user should save all data space registers which may be used within the interrupt routines. the following list summarizes the interrupt proce - dure: when an interrupt request occurs, the following actions are performed by the mcu automatically: ? the core switches from the normal flags to the interrupt flags (or the nmi flags). ? the pc contents are stored in the top level of the stack. ? the normal interrupt lines are inhibited (nmi still active). ? the internal latch (if any) is cleared. ? the associated interrupt vector is loaded in the pc. when an interrupt request occurs, the following actions must be performed by the user software: ? user selected registers have to be saved within the interrupt service r outine (normally on a soft - ware stack). ? the source of the interrupt must be determined by polling the interrupt flags (if more than one source is associated with the same vector). ? the reti (return from interrupt) instruction must end the interrupt service routine. after the reti instruction is executed, the mcu re - turns to the main routine. caution: when a maskable interrupt occurs while the st6 core is in normal mode and during the execution of an ?ldi ior, 00h? instruction (disabling all maskable interrupts): if the interrupt request oc - curs during the first 3 cycles of the ?ldi? instruction (which is a 4-cycle instruct ion) the core will switch to interrupt mode but the flags cn and zn will not switch to the interrupt pair ci and zi. 5.10.1 interrupt response time this is defined as the time between the moment when the program counter is loaded with the in - terrupt vector and when the program has jump to the interrupt subroutine and is ready to execute the code. it depends on when the interrupt occurs while the core is processing an instruction. figure 18. interrupt processing flow chart table 6. interrupt response time one cpu cycle is 13 external clock cycles thus 11 cpu cycles = 11 x (13 /8m) = 17.875 s with an 8 mhz external quartz. minimum 6 cpu cycles maximum 11 cpu cycles instruction fetch instruction execute instruction was the instruction a reti ? enable maskable interrupts select normal flags ?pop? the stacked pc is there an an interrupt request and interrupt mask? select interrupt flags push the pc into the stack load pc from interrupt vector disable maskable interrupt no no yes is the core already in normal mode? yes no yes clear internal latch *) *) if a latch is present on the interrupt source line 1
st6200c st6201c st6203c 30/100 doc id 4563 rev 5 5.11 register description interrupt option register (ior) address: 0c8h ? write only reset status: 00h caution: this register is write-only and cannot be accessed by single-bit operations (set, res, dec,...). bit 7 =reserved, must be cleared. bit 6 = les level/edge selection bit . 0: falling edge sensitive mode is selected for inter - rupt vector #1 1: low level sensitive mode is selected for inter - rupt vector #1 bit 5 = esb edge selection bit . 0: falling edge mode on interrupt vector #2 1: rising edge mode on interrupt vector #2 bit 4 = gen global enable interrupt . 0: disable all maskable interrupts 1: enable all maskable interrupts note: when the gen bit is cleared, the nmi inter - rupt is active but cannot be used to exit from stop or wait modes. bits 3:0 = reserved, must be cleared. table 7. interrupt mapping * depending on device. see device summary on page 1. 7 0 - les esb gen - - - - vector number source block description register label flag exit from stop vector address priority order reset reset n/a n/a yes ffeh-fffh vector #0 nmi non maskable interrupt n/a n/a yes ffch-ffdh not used ffah-ffbh ff8h-ff9h vector #1 port a ext. interrupt port a n/a n/a yes ff6h-ff7h vector #2 port b ext. interrupt port b n/a n/a yes ff4h-ff5h vector #3 timer timer underflow tscr tmz yes ff2h-ff3h vector #4 adc * end of conversion adcr eoc no ff0h-ff1h priority lowest highest priority 1
st6200c st6201c st6203c doc id 4563 rev 5 31/100 6 power saving modes 6.1 introduction to give a large measure of flexibility to the applica - tion in terms of power consumption, two main pow - er saving modes are impl emented in the st6 (see figure 19 ). in addition, the low frequen cy auxiliary oscillator (lfao) can be used instead of the main oscillator to reduce power consumption in run and wait modes. after a reset the normal operating mode is se - lected by default (run mode). this mode drives the device (cpu and embedded peripherals) by means of a master cloc k which is based on the main oscillator frequency. from run mode, the different power saving modes may be selected by calling the specific st6 software instruction or for the lfao by setting the relevant register bit. for more information on the lfao, please refer to the clock chapter. figure 19. power saving mode transitions power consumption wait lfao run stop high low 1
st6200c st6201c st6203c 32/100 doc id 4563 rev 5 6.2 wait mode the mcu goes into wait mode as soon as the wait instruction is executed. this has the follow - ing effects: ? program execution is stopped, the microcontrol - ler software can be considered as being in a ?fro - zen? state. ? ram contents and peri pheral registers are pre - served as long as the pow er supply voltage is higher than the ram retention voltage. ? the oscillator is kept running to provide a clock to the peripherals; t hey are still active. wait mode can be used when the user wants to reduce the mcu power consumption during idle periods, while not losing trac k of time or the ability to monitor external events. wait mode places the mcu in a low power consumption mode by stop - ping the cpu. the active os cillator (main oscillator or lfao) is kept running in order to provide a clock signal to the peripherals. if the power consumption has to be further re - duced, the low frequency auxiliary oscillator (lfao) can be used in place of the main oscillator, if its operating frequency is lower. if required, the lfao must be switched on before entering wait mode. exit from wait mode the mcu remains in wait mode until one of the following events occurs: ? reset (watchdog, lvd or reset pin) ? a peripheral interrupt (timer, adc,...), ? an external interrupt (i/o port, nmi) the program counter then branches to the start - ing address of the interrupt or reset service rou - tine. refer to figure 20 . see also section 6.4.1 . figure 20. wait mode flowchart wait instruction reset interrupt y n n y clock to cpu oscillator clock to peripherals on yes no fetch reset vector or service interrupt 2048 clock to cpu oscillator clock to peripherals restart yes yes delay clock cycle oscillator clock to peripherals clock to cpu yes yes on 1
st6200c st6201c st6203c doc id 4563 rev 5 33/100 6.3 stop mode stop mode is the lowest power consumption mode of the mcu (see figure 22 ). the mcu goes into stop mode as soon as the stop instruction is exec uted. this has the follow - ing effects: ? program execution is stopped, the microcontrol - ler can be considered as being ?frozen?. ? the contents of ram and the peripheral regis - ters are kept safely as long as the power supply voltage is higher than the ram retention voltage. ? the oscillator is stopped, so peripherals cannot work except the those that can be driven by an external clock. exit from stop mode the mcu remains in stop mode until one of the following events occurs: ? reset (watchdog, lvd or reset pin) ? a peripheral interrupt (a ssuming this peripheral can be driven by an external clock) ? an external interrupt (i/o port, nmi) in all cases a delay of 2048 clock cycles (f int ) is generated to make sure the oscillator has started properly. the program counter then points to the starting address of the interrupt or reset service routine (see figure 21 ). stop mode and watchdog when the watchdog is active (hardware or soft - ware activation), the stop instruction is disabled and a wait instruction will be executed in its place unless the exctnl option bit is set to 1 in the op - tion bytes and a a high level is present on the nmi pin. in this case, the stop instruction will be exe - cuted and the watchdog will be frozen. figure 21. stop mode timing overview stop run run 2048 reset or interrupt stop instruction fetch vector cycle clock delay 1
st6200c st6201c st6203c 34/100 doc id 4563 rev 5 stop mode (cont?d) figure 22. stop mode flowchart notes: 1. exctnl is an option bit. see opti on byte section for more details. 2. peripheral clocked with an external clock source can still be active. 3. only some specific interrupts can exit the mcu fr om stop mode (such as external interrupt). refer to the interrupt mapping table for more details. stop instruction reset interrupt 3) y n n y fetch reset vector or service interrupt watchdog enable disable exctnl 1 1 level on nmi pin 0 0 reset interrupt n n y y value 1) clock to cpu oscillator clock to peripherals 2) off no no 2048 delay clock to cpu oscillator clock to peripherals restart yes yes clock to cpu oscillator clock to peripherals on yes yes clock to cpu oscillator clock to peripherals on yes no clock cycle 1
st6200c st6201c st6203c doc id 4563 rev 5 35/100 6.4 notes related to wait and stop modes 6.4.1 exit from wait and stop modes 6.4.1.1 nmi interrupt it should be noted that when the gen bit in the ior register is low (int errupts disabled), the nmi interrupt is active but c annot cause a wake up from stop/wait modes. 6.4.1.2 restart sequence when the mcu exits from wait or stop mode, it should be noted that the restart sequence de - pends on the original state of the mcu (normal, in - terrupt or non-maskable interrupt mode) prior to entering wait or stop mode, as well as on the interrupt type. normal mode. if the mcu was in the main routine when the wait or stop instruction was execut - ed, exit from stop or wait mode will occur as soon as an interrupt occurs; the related interrupt routine is executed and, on completion, the instruction which follows the stop or wait instruction is then executed, providing no other interrupts are pending. non maskable interrupt mode. if the stop or wait instruction has been executed during execu - tion of the non-maskable interrupt routine, the mcu exits from stop or wait mode as soon as an interrupt occurs: the instruction which follows the stop or wait instruction is executed, and the mcu remains in non-maskable interrupt mode, even if another interrupt has been generated. normal interrupt mode. if the mcu was in inter - rupt mode before the stop or wait instruction was executed, it exits from stop or wait mode as soon as an interrupt oc curs. nevertheless, two cases must be considered: ? if the interrupt is a normal one, the interrupt rou - tine in which the wait or stop mode was en - tered will be completed, starting with the execution of the instruction which follows the stop or the wait instruction, and the mcu is still in interrupt mode. at the end of this routine pending interrupts will be serviced according to their priority. ? in the event of a non-maskable interrupt, the non-maskable interrupt se rvice routine is proc - essed first, then the routine in which the wait or stop mode was entered will be completed by executing the instruction following the stop or wait instruction. the mcu remains in normal in - terrupt mode. 6.4.2 recommended mcu configuration for lowest power consumption during run or wait modes, the user software must configure the mcu as follows: ? configure unused i/os as output push-pull low mode ? place all peripherals in their power down modes before entering stop mode ? select the low frequenc y auxiliary oscillator (provided this runs at a lower frequency than the main oscillator). the wait and stop instructions are not execut - ed if an enabled interrupt request is pending. 1
st6200c st6201c st6203c 36/100 doc id 4563 rev 5 7 i/o ports 7.1 introduction each i/o port contains up to 8 pins. each pin can be programmed independently as digital input (with or without pull-up and interrupt generation), digital output (open drain, push-pull) or analog in - put (when available). the i/o pins can be used in either standard or al - ternate function mode. standard i/o mode is used for: ? transfer of data through digital inputs and out - puts (on specific pins): ? external interrupt generation alternate function mode is used for: ? alternate signal input/output for the on-chip peripherals the generic i/o block diagram is shown in figure 23 . 7.2 functional description each port is associated with 3 registers located in data space: ? data register (dr) ? data direction register (ddr) ? option register (or) each i/o pin may be programmed using the corre - sponding register bits in the ddr, dr and or reg - isters: bit x corresponding to pin x of the port. table 8 illustrates the various port configurations which can be selected by user software. during mcu initialization, all i/o r egisters are cleared and the input mode with pull-up and no in - terrupt generation is selected for all the pins, thus avoiding pin conflicts. 7.2.1 digital input modes the input configuration is selected by clearing the corresponding ddr register bit. in this case, reading the dr register returns the digital value applied to the external i/o pin. different input modes can be selected by software through the dr and or registers, see table 8 . external interrupt function all input lines can be i ndividually connected by software to the interrupt system by programming the or and dr registers accordingly. the inter - rupt trigger modes (falling edge, rising edge and low level) can be configured by software for each port as described in the interrupt section. 7.2.2 analog inputs some pins can be confi gured as analog inputs by programming the or and dr registers according - ly, see table 8 . these analog inputs are connect - ed to the on-chip 8-bit analog to digital converter. caution: only one pin should be programmed as an analog input at any time, since by selecting more than one input simult aneously their pins will be effectively shorted. 7.2.3 output modes the output configuration is selected by setting the corresponding ddr register bit. in this case, writ - ing to the dr register appl ies this digital value to the i/o pin through the latch. then, reading the dr register returns the previously stored value. two different output modes can be selected by software through the or register: push-pull and open-drain. dr register value and output pin status: note : the open drain setting is not a true open drain. this means it has the same structure as the push-pull setting but the p-buffer is deactivated. to avoid damaging the dev ice, please respect the v out absolute maximum rating described in the electrical charac teristics section. 7.2.4 alternate functions when an on-chip peripheral is configured to use a pin, the alternate function (timer input/output...) is not systematically selected but has to be config - ured through the ddr, or and dr registers. re - fer to the chapter describing the peripheral for more details. dr push-pull open-drain 0 v ss v ss 1 v dd floating 1
st6200c st6201c st6203c doc id 4563 rev 5 37/100 i/o ports (cont?d) figure 23. i/o port block diagram table 8. i/o port configurations note: x = don?t care ddr or dr mode option 0 0 0 input with pull-up, no interrupt 0 0 1 input no pull-up, no interrupt 0 1 0 input with pull-up and with interrupt 0 1 1 input analog input (when available) 1 0 x output open-drain output (20ma sink when available) 1 1 x output push-pull output (20ma sink when available) v dd reset st6 internal data data direction register register option register to interrupt v dd to adc v dd n-buffer p-buffer pull-up cmos schmitt trigger pxx i/o pin bus clamping diodes * * depending on device. see device summary on page 1 . 1
st6200c st6201c st6203c 38/100 doc id 4563 rev 5 i/o ports (cont?d) 7.2.5 instructions not to be used to access port data registers (set, res, inc and dec) do not use read-modify-write instruc - tions (set, res, inc and dec) on port data registers if any pin of the port is configured in input mode. these instructions make an implicit read and write back of the entire register. in port input mode, however, the data register reads from the input pins directly, and not from the data register latch - es. since data register info rmation in input mode is used to set the characteristics of the input pin (in - terrupt, pull-up, analog input), these may be unin - tentionally reprogrammed depending on the state of the input pins. as a general rule, it is better to only use single bit instructions on data regi sters when the whole (8- bit) port is in output mode. in the case of inputs or of mixed inputs and outputs, it is advisable to keep a copy of the data register in ram. single bit in - structions may then be used on the ram copy, af - ter which the whole copy r egister can be written to the port data register: set bit, datacopy ld a, datacopy ld dra, a 7.2.6 recommendations 1. safe i/o state switching sequence switching the i/o ports from one state to another should be done in a sequence which ensures that no unwanted side effects can occur. the recom - mended safe transitions are illustrated in figure 24 the interrupt pull-up to input analog transition (and vice-vesra) is potentially risky and should be avoided when changing t he i/o operating mode. 2. handling unused port bits on ports that have less than 8 external pins con - nected: ? leave the unbonded pins in reset state and do not change their configuration. ? do not use instructions that act on a whole port register (inc, dec, or read operations). unavail - able bits must be masked by software (and in - struction). thus, when a read operation performed on an incomplete port is followed by a comparison, use a mask. 3. high impedance input on any cmos device, it is not recommended to connect high impedance on input pins. the choice of these impedance has to be done with respect to the maximum leakage current defined in the da - tasheet. the risk is to be close or out of specifica - tion on the input levels applied to the device. 7.3 low power modes the wait and stop instructions allow the st62xx to be used in situations where low power consumption is needed. the lowest power con - sumption is achieved by configuring i/os in output push-pull low mode. 7.4 interrupts the external interrupt ev ent generates an interrupt if the corresponding configuration is selected with ddr, dr and or registers (see table 8 ) and the gen-bit in the ior register is set. figure 24. diagram showing safe i/o state transitions note *. xxx = ddr, or, dr bits respectively mode description wait no effect on i/o ports. external interrupts cause the device to exit from wait mode. stop no effect on i/o ports. external interrupts cause the device to exit from stop mode. interrupt pull-up output open drain output push-pull input pull-up (reset state) input analog output open drain output push-pull input 010* 000 100 110 011 001 101 111 1
st6200c st6201c st6203c doc id 4563 rev 5 39/100 i/o ports (cont?d) table 9. i/o port option selections note 1 . provided the correct confi guration has been selected (see table 8 ). mode available on (1) schematic digital input input pa1-pa3 pb0, pb1, pb3, pb5-pb7 ddrx 0 orx 0 drx 1 reset state input with pull up pa1-pa3 pb0, pb1, pb3, pb5-pb7 ddrx 0 orx 0 drx 0 input with pull up with interrupt pa1-pa3 pb0, pb1, pb3, pb5-pb7 ddrx 0 orx 1 drx 0 analog input analog input pb3, pb5-pb7 (except on st6203c ) ddrx 0 orx 1 drx 1 digital output open drain output (5ma) open drain output (20 ma) pb0, pb1, pb3, pb5-pb7 pa1-pa3 ddrx 1 orx 0 drx 0/1 push-pull output (5ma) push-pull output (20 ma) pb0, pb1, pb3, pb5-pb7 pa1-pa3 ddrx 1 orx 1 drx 0/1 data in interrupt v dd v dd data in interrupt v dd v dd data in interrupt v dd v dd adc v dd data out p-buffer disconnected v dd data out v dd 1
st6200c st6201c st6203c 40/100 doc id 4563 rev 5 i/o ports (cont?d) 7.5 register description data register (dr) port x data register drx with x = a or b. address dra: 0c0h - read / write address drb: 0c1h - read / write reset value: 0000 0000 (00h) bit 7:0 = d[7:0] data register bits. reading the dr register returns either the dr reg - ister latch content (pin configured as output) or the digital value applied to t he i/o pin (pin configured as input). caution: in input mode, modifyin g this register will modify the i/o port configuration (see table 8 ). do not use the single bit instructions on i/o port data registers. see ( section 7.2.5 ). data direction register (ddr) port x data direction register ddrx with x = a or b. address ddra: 0c4h - read / write address ddrb: 0c5h - read / write reset value: 0000 0000 (00h) bit 7:0 = dd[7:0] data direction register bits. the ddr register gives the input/output direction configuration of the pins. each bit is set and cleared by software. 0: input mode 1: output mode option register (or) port x option register orx with x = a or b. address ora: 0cch - read / write address orb: 0cdh - read / write reset value: 0000 0000 (00h) bit 7:0 = o[7:0] option register bits. the or register allows to distinguish in output mode if the push-pull or op en drain configuration is selected. output mode: 0: open drain output(with p-buffer deactivated) 1: push-pull output input mode: see table 8 . each bit is set and cleared by software. caution: modifying this register , will also modify the i/o port configuration in input mode. (see ta - ble 8 ). table 10. i/o port register map and reset values 7 0 d7 d6 d5 d4 d3 d2 d1 d0 7 0 dd7 dd6 dd5 dd4 dd3 dd2 dd1 dd0 7 0 o7 o6 o5 o4 o3 o2 o1 o0 address (hex.) register label 7 6 5 4 3 2 1 0 reset value of all i/o port registers 0 0 0 0 0 0 0 0 0c0h dra msb lsb 0c1h drb 0c4h ddra msb lsb 0c5h ddrb 0cch ora msb lsb 0cdh orb 1
st6200c st6201c st6203c doc id 4563 rev 5 41/100 8 on-chip peripherals 8.1 watchdog timer (wdg) 8.1.1 introduction the watchdog timer is used to detect the occur - rence of a software fault, usually generated by ex - ternal interference or by unforeseen logical condi - tions, which causes the application program to abandon its normal sequence. the watchdog cir - cuit generates an mcu reset on expiry of a pro - grammed time period, unl ess the program refresh - es the counter?s contents before the sr bit be - comes cleared. 8.1.2 main features programmable timer (64 steps of 3072 clock cycles) software reset reset (if watchdog activated) when the sr bit reaches zero hardware or software watchdog activation selectable by option bit (refer to the option bytes section) figure 25. watchdog block diagram reset c 7-bit downcounter f int /12 sr t0 clock divider watchdog register (wdgr) 256 t1 t2 t3 t4 t5 bit 0 bit 7 1
st6200c st6201c st6203c 42/100 doc id 4563 rev 5 watchdog timer (cont?d) 8.1.3 functional description the watchdog activation is selected through an option in the option bytes: ? hardware watchdog option after reset, the watchdog is permanently active, the c bit in the wdgr is forced high and the user can not change it. however, this bit can be read equally as 0 or 1. ? software watchdog option after reset, the watchdog is deactivated. the func - tion is activated by setting c bit in the wdgr reg - ister. once activated, it cannot be deactivated. the counter value stored in the wdgr register (bits sr:t0), is decremented every 3072 clock cy - cles. the length of the timeout period can be pro - grammed by the user in 64 steps of 3072 clock cy - cles. if the watchdog is activated (by setting the c bit) and when the sr bit is cleared, the watchdog initi - ates a reset cycle pulling the reset pin low for typi - cally 500ns. the application program must write in the wdgr register at regular intervals during normal opera - tion to prevent an mcu reset. the value to be stored in the wdgr register must be between feh and 02h (see table 11 ). to run the watchdog function the following conditions must be true: ? the c bit is set (watchdog activated) ? the sr bit is set to prevent generating an imme - diate reset ? the t[5:0] bits contain the number of decre - ments which represent the time delay before the watchdog produces a reset. table 11. watchdog timing (f osc = 8 mhz ) 8.1.3.1 software reset the sr bit can be used to generate a software re - set by clearing the sr bit while the c bit is set. 8.1.4 recommendations 1. the watchdog plays an important supporting role in the high noise immunity of st62xx devices, and should be used wherever possible. watchdog related options should be selected on the basis of a trade-off between application security and stop mode availability (refer to the description of the wdact and extcntl bits on the option bytes). when stop mode is not required, hardware acti - vation without external stop mode con - trol should be preferred, as it provides maxi - mum security, especia lly during power-on. when stop mode is required, hardware activa - tion and external stop mode control should be chosen. nmi should be high by default, to allow stop mode to be entered when the mcu is idle. the nmi pin can be connected to an i/o line (see figure 26 ) to allow its state to be controlled by soft - ware. the i/o line can then be used to keep nmi low while watchdog protecti on is required, or to avoid noise or key bounce. when no more processing is required, th e i/o line is released and the device placed in stop mode for lowest power consumption. figure 26. a typical circuit making use of the exernal stop mode control feature 2. when software activation is selected (wdact bit in option byte) and the watchdog is not activat - ed, the downcounter may be used as a simple 7- bit timer (remember that t he bits are in reverse or - der). the software activation option should be chosen only when the watchdog counter is to be used as a timer. to ensure the watchdog has not been un - expectedly activated, the following instructions should be executed: jrr 0, wdgr, #+3 ; if c=0,jump to next ldi wdgr, 0fdh ; sr=0 -> reset next : wdgr register initial value wdg timeout period (ms) max. feh 24.576 min. 02h 0.384 nmi switch i/o vr02002 1
st6200c st6201c st6203c doc id 4563 rev 5 43/100 watchdog timer (cont?d) these instructions test the c bit and reset the mcu (i.e. disable the watchdog) if the bit is set (i.e. if the watchdog is active), thus disabling the watchdog. for more information on the use of the watchdog, please read application note an1015. note: this note applies only when the watchdog is used as a standard timer. it is recommended to read the counter twice, as it may sometimes return an invalid value if the read is performed while the counter is decremented (coun ter bits in transient state). to validate the return value, both values read must be equal. the counter decrements eve - ry 384 s at 8 mhz f osc . 8.1.5 low power modes 8.1.6 interrupts none. mode description wait no effect on watchdog. stop behaviour depends on the extcntl option in the option bytes: 1. watchdog disabled: the mcu will enter stop mode if a stop instruction is executed. 2. watchdog enabled and extcntl option disabled: if a stop instruction is encounter ed, it is interpreted as a wait. 3. watchdog and extcntl option enabled: if a stop instruction is encountered when the nmi pin is low, it is interpreted as a wait. if, however, the stop instruction is encountered when the nmi pin is high, the watchdog counter is frozen and the cpu en - ters stop mode. when the mcu exits stop mode (i.e. when an interrupt is generated), the watchdog resumes its activity. 1
st6200c st6201c st6203c 44/100 doc id 4563 rev 5 watchdog timer (cont?d) 8.1.7 register description watchdog register (wdgr) address: 0d8h - read / write reset value: 1111 1110 (fe h) bits 7:2 = t[5:0] downcounter bits caution: these bits are reversed and shifted with respect to the physical c ounter: bit-7 (t0) is the lsb of the watchdog downcounter and bit-2 (t5) is the msb. bit 1 = sr : software reset bit software can generate a reset by clearing this bit while the c bit is set. when c = 0 (watchdog de - activated) the sr bit is the msb of the 7-bit timer. 0: generate (write) 1: no software reset generated, msb of 7-bit timer bit 0 = c watchdog control bit . if the hardware option is selected (wdact bit in option byte), this bit is forced high and cannot be changed by the user (the watchdog is always ac - tive). when the software option is selected (wdact bit in option byte), the watchdog func - tion is activated by setting the c bit, and cannot then be deactivated (except by resetting the mcu). when c is kept cleared the counter can be used as a 7-bit timer. 0: watchdog deactivated 1: watchdog activated 7 0 t0 t1 t2 t3 t4 t5 sr c 1
st6200c st6201c st6203c doc id 4563 rev 5 45/100 8.2 8-bit timer 8.2.1 introduction the 8-bit timer on-chip peripheral is a free run - ning downcounter based on an 8-bit downcounter with a 7-bit programmable prescaler, giving a max - imum count of 2 15 . 8.2.2 main features time-out downcounting mode with up to 15-bit accuracy interrupt capability on counter underflow the timer can be used in wait mode to wake up the mcu. figure 27. timer block diagram interrupt tmz eti tscr5 tscr4 psi ps2 ps1 ps0 tscr programmable prescaler pscr6 pscr5 pscr4 pscr3 pscr2 pscr1 pscr0 pscr register 0 70 tcr7 tcr6 tcr5 tcr4 tcr3 tcr2 tcr1 tcr0 tcr 70 reload 8-bit down counter f prescaler f counter f int/12 pscr7 7 /2 /1 /4 /8 /16 /32 /64 /128 register register 1
st6200c st6201c st6203c 46/100 doc id 4563 rev 5 8-bit timer (cont?d) 8.2.3 counter/prescaler description prescaler the prescaler input is the internal frequency f int divided by 12. the prescaler decrements on the rising edge, depending on the division factor pro - grammed by the ps[2:0] bits in the tscr register. the state of the 7-bit prescaler can be read in the pscr register. when the prescaler reaches 0, it is automatically reloaded with 7fh. counter the free running 8-bit downcounter is fed by the output of the programmable prescaler, and is dec - remented on every rising edge of the f counter clock signal coming from the prescaler. it is possible to read or write the contents of the counter on the fly, by reading or writing the timer counter register (tcr). when the downcounter reaches 0, it is automati - cally reloaded with the value 0ffh. counter clock and prescaler the counter clock fr equency is given by: f counter = f prescaler / 2 ps[2:0] where f prescaler is: ?f int /12 the timer input clock f eeds the 7-bit programma - ble prescaler. the prescaler output can be pro - grammed by selecting one of the 8 available pres - caler taps using the ps[2:0] bits in the status/con - trol register (tscr). thus the division factor of the prescaler can be set to 2 n (where n equals 0, to 7). see figure 27 . the clock input is enabled by the psi (prescaler initialize) bit in the ts cr register. when psi is re - set, the counter is frozen and the prescaler is load - ed with the value 7fh. when psi is set, the pres - caler and the counter run at the rate of the select - ed clock source. counter and prescaler initialization after reset, the counter and the prescaler are in - itialized to 0ffh and 7fh respectively. the 7-bit prescaler can be initialized to 7fh by clearing the psi bit. direct write access to the prescaler is also possible when psi =1. then, any value between 0 and 7fh can be loaded into it. the 8-bit counter can be in itialized separately by writing to the tcr register. 8.2.3.1 8-bit counting and interrupt capability on counter underflow whatever the division factor defined for the pres - caler, the timer counter works as an 8-bit down - counter. the input clock frequency is user selecta - ble using the ps[2:0] bits. when the downcounter decrements to zero, the tmz (timer zero) bit in the tscr is set. if the eti (enable timer interrupt) bi t in the tscr is also set, an interrupt request is generated. the timer interrupt can be used to exit the mcu from wait or stop mode. the tcr can be written at any time by software to define a time period ending with an underflow event, and therefore manag e delay or timer func - tions. tmz is set when the downcounter reaches zero; however, it may also be set by writing 00h in the tcr register or by setting bit 7 of the tscr register. the tmz bit must be cl eared by user software when servicing the timer interrupt to avoid unde - sired interrupts when leavi ng the interrupt service routine. note : a write to the tcr register will predominate over the 8-bit counter de crement to 00h function, i.e. if a write and a tcr register decrement to 00h occur simultaneously, the write will take prece - dence, and the tmz bit is not set until the 8-bit counter underflows again. 8.2.4 low power modes 8.2.5 interrupts mode description wait no effect on timer. timer interrupt events cause the device to exit from wait mode. stop timer registers are frozen. interrupt event event flag enable bit exit from wait exit from stop timer zero event tmz eti yes no 1
st6200c st6201c st6203c doc id 4563 rev 5 47/100 8-bit timer (cont?d) 8.2.6 register description prescaler counter register (pscr) address: 0d2h - read/write reset value: 0111 1111 (7fh) bit 7 = pscr7: not used, always read as ?0?. bits 6:0 = pscr[6:0] prescaler lsb. timer counter register (tcr) address: 0d3h - read / write reset value: 1111 1111 (ffh) bits 7:0 = tcr[7:0] timer counter bits. timer status control register (tscr) address: 0d4h - read/write reset value: 0000 0000 (00h) bit 7 = tmz timer zero bit. a low-to-high transition indicates that the timer count register has underfl owed. it means that the tcr value has changed from 00h to ffh. this bit must be cleared by user software. 0: counter has not underflowed 1: counter underflow occurred bit 6 = eti enable timer interrupt. when set, enables the timer interrupt request. if eti=0 the timer interrupt is disabled. if eti=1 and tmz=1 an interrupt request is generated. 0: interrupt disabled (reset state) 1: interrupt enabled bit 5 = tscr5 reserved , must be set. bit 4 = tscr4 reserved , must be cleared. bit 3 = psi : prescaler initialize bit. used to initialize the prescaler and inhibit its count - ing. when psi=?0? the prescaler is set to 7fh and the counter is inhibited. when psi=?1? the prescal - er is enabled to count downwards. as long as pse=?1? both counter and prescaler are not run - ning 0: counting disabled 1: counting enabled bits 1:0 = ps[2:0] prescaler mux. select. these bits select the division ratio of the prescaler register. table 12. prescaler division factors table 13. 8-bit timer register map and reset values 7 0 pscr 7 pscr 6 pscr 5 pscr 4 pscr 3 pscr 2 pscr 1 pscr 0 7 0 tcr7 tcr6 tcr5 tcr4 tcr3 tcr2 tcr1 tcr0 7 0 tmz eti tscr5 tscr4 psi ps2 ps1 ps0 ps2 ps1 ps0 divided by 0 0 0 1 0 0 1 2 0 1 0 4 0 1 1 8 1 0 0 16 1 0 1 32 1 1 0 64 1 1 1 128 address (hex.) register label 7 6 5 4 3 2 1 0 0d2h pscr reset value pscr7 0 pscr6 1 pscr5 1 pscr4 1 pscr3 1 pscr2 1 pscr1 1 pscr0 1 0d3h tcr reset value tcr7 1 tcr6 1 tcr5 1 tcr4 1 tcr3 1 tcr2 1 tcr1 1 tcr0 1 0d4h tscr reset value tmz 0 eti 0 tscr5 0 tscr4 0 psi 0 ps2 0 ps1 0 ps0 0 1
st6200c st6201c st6203c 48/100 doc id 4563 rev 5 8.3 a/d converter (adc) 8.3.1 introduction the on-chip analog to di gital converter (adc) pe - ripheral is a 8-bit, succ essive approximation con - verter. this peripheral has multiplexed analog in - put channels (refer to device pin out description) that allow the peripheral to convert the analog volt - age levels from different sources. the result of the conversion is stored in a 8-bit data register. the a/d converter is controlled through a control register. 8.3.2 main features 8-bit conversion multiplexed analog input channels linear successive approximation data register (dr) whic h contains the results end of conversion flag on/off bit (to reduce consumption) typical conversion time 70 s (with an 8 mhz crystal) the block diagram is shown in figure 28 . figure 28. adc block diagram note: adc not present on some devic es. see device summary on page 1. osc ad eai eoc sta pds adcr ain0 ain1 analog to digital converter ainx port mux adr2 adr1 adr3 adr7 adr6 adr5 adr4 adr0 adr div 12 f adc f int ddrx orx drx i/o port off cr3 ad cr1 ad cr0 1
st6200c st6201c st6203c doc id 4563 rev 5 49/100 a/d converter (cont?d) 8.3.3 functional description 8.3.3.1 analog power supply the high and low level refe rence voltage pins are internally connected to the v dd and v ss pins. conversion accuracy may therefore be impacted by voltage drops and noise in the event of heavily loaded or badly decoupled power supply lines. 8.3.3.2 digital a/d conversion result the conversion is monotonic, meaning that the re - sult never decreases if the analog input does not and never increases if the analog input does not. if the input voltage (v ain ) is greater than or equal to v dda (high-level voltage reference) then the conversion result in the dr register is ffh (full scale) without overflow indication. if input voltage (v ain ) is lower than or equal to v ssa (low-level voltage reference) then the con - version result in the dr register is 00h. the a/d converter is linear and the digital result of the conversion is stored in the adr register. the accuracy of the conversion is described in the par - ametric section. r ain is the maximum recommended impedance for an analog input signal. if the impedance is too high, this will result in a loss of accuracy due to leakage and sampling not being completed in the allocated time. refer to t he electrical characteris - tics chapter for more details. with an oscillator cl ock frequency less than 1.2mhz, conversion accuracy is decreased. 8.3.3.3 analog input selection selection of the input pin is done by configuring the related i/o line as an analog input via the data direction, option and data registers (refer to i/o ports description for additional information). caution: only one i/o line must be configured as an analog input at any time. the user must avoid any situation in which more than one i/o pin is se - lected as an analog input simultaneously, because they will be shor ted internally. 8.3.3.4 software procedure refer to the control register (adcr) and data reg - ister (adr) in section 8.3.7 for the bit definitions. analog input configuration the analog input must be configured through the port control registers (ddrx, orx and drx). re - fer to the i/o port chapter. adc configuration in the adcr register: ? reset the pds bit to power on the adc. this bit must be set at least one instruction before the beginning of the conversion to allow stabilisation of the a/d converter. ? set the eai bit to enable the adc interrupt if needed. adc conversion in the adcr register: ? set the sta bit to start a conversion. this auto - matically clears (resets to ?0?) the end of con - version bit (eoc). when a conversion is complete ? the eoc bit is set by hardware to flag that con - version is complete and that the data in the adc data conversion register is valid. ? an interrupt is generated if the eai bit was set setting the sta bit will st art a new count and will clear the eoc bit (thus clearing the interrupt con - dition) note: setting the sta bit must be done by a different in - struction from the instruction that powers-on the adc (setting the pds bit) in order to make sure the voltage to be converted is present on the pin. each conversion has to be separately initiated by writing to the sta bit. the sta bit is continuously scanned so that, if the user sets it to ?1? while a previous conversion is in progress, a new conversi on is started before com - pleting the previous one. the start bit (sta) is a write only bit, any attempt to read it will show a log - ical ?0?. 1
st6200c st6201c st6203c 50/100 doc id 4563 rev 5 a/d converter (cont?d) 8.3.4 recommendations the following six notes provide additional informa - tion on using the a/d converter. 1.the a/d converter does not feature a sample and hold circuit. the analog voltage to be meas - ured should therefore be stable during the entire conversion cycle. voltage variation should not ex - ceed 1/2 lsb for optimum conversion accuracy. a low pass filter may be used at the analog input pins to reduce input voltage variation during con - version. 2. when selected as an analog channel, the input pin is internally connec ted to a capacitor c ad of typically 9pf. for maximu m accuracy, this capaci - tor must be fully charged at the beginning of con - version. in the worst case, conversion starts one instruction (6.5 s) after the channel has been se - lected. the impedance of the analog voltage source (asi) in worst ca se conditions, is calculat - ed using the following formula: 6.5s = 9 x c ad x asi (capacitor charged to over 99.9%), i.e. 30 k in - cluding a 50% guardband. the asi can be higher if c ad has been charged for a longer period by adding instructions before the start of conversion (adding more than 26 cpu cy - cles is pointless). 3. since the adc is on the same chip as the micro - processor, the user should not switch heavily load - ed output signals during conv ersion, if high preci - sion is required. such switching will affect the sup - ply voltages used as analog references. 4. conversion accuracy depends on the quality of the power supplies (v dd and v ss ). the user must take special care to ensure a well regulated refer - ence voltage is present on the v dd and v ss pins (power supply voltage variations must be less than 0.1v/ms). this implies, in particular, that a suitable decoupling capacitor is used at the v dd pin. the converter resolu tion is given by: the input voltage (ain) which is to be converted must be constant for 1s before conversion and remain constant during conversion. 5. conversion resolution can be improved if the power supply voltage (v dd ) to the microcontroller is lowered. 6. in order to optimize the conversion resolution, the user can configure the microcontroller in wait mode, because this mode minimises noise distur - bances and power supply variations due to output switching. nevertheless, the wait instruction should be executed as s oon as possible after the beginning of the conversion , because execution of the wait instruction may cause a small variation of the v dd voltage. the negative effect of this var - iation is minimized at the beginning of the conver - sion when the converter is less sensitive, rather than at the end of conversion, when the least sig - nificant bits are determined. the best configuration, from an accuracy stand - point, is wait mode with the timer stopped. in this case only the adc peripheral and the oscilla - tor are then still working. the mcu must be woken up from wait mode by the adc interrupt at the end of the conversion. th e microcontroller can also be woken up by the timer interrupt, but this means the timer must be running and the result - ing noise could affect conversion accuracy. caution: when an i/o pin is used as an analog in - put, a/d conversion accura cy will be impaired if negative current injections (v inj < v ss ) occur from adjacent i/o pins with analog input capability. re - fer to figure 29 . to avoid this: ? use another i/o port located further away from the analog pin, preferably not multiplexed on the a/d converter ? increase the input resistance r in j (to reduce the current injections) and reduce r adc (to preserve conversion accuracy). figure 29. leakage from digital inputs v dd v ss ? 256 ------------------------------- - pby/ainy pbx/ainx r adc leakage current if v inj < v ss a/d i/o port (digital i/o) r inj converter digital input analog input v ain v inj 1
st6200c st6201c st6203c doc id 4563 rev 5 51/100 a/d converter (cont?d) 8.3.5 low power modes note : the a/d converter may be disabled by clear - ing the pds bit. this feature allows reduced power consumption when no conversion is needed. 8.3.6 interrupts note: the eoc bit is cleared only when a new conversion is started (i t cannot be cleared by writ - ing 0). to avoid generati ng further eoc interrupt, the eai bit has to be cleared within the adc inter - rupt subroutine. 8.3.7 register description a/d converter control register (ad - cr) address: 0d1h - read/write (bit 6 read only, bit 5 write only) reset value: 0100 0000 (40h) bit 7 = eai enable a/d interrupt. 0: adc interrupt disabled 1: adc interrupt enabled bit 6 = eoc end of conversion. read only when a conversion has been completed, this bit is set by hardware and an interrupt request is gener - ated if the eai bit is set. the eoc bit is automati - cally cleared when the sta bit is set. data in the data conversion register are valid only when this bit is set to ?1?. 0: conversion is not complete 1: conversion can be read from the adr register bit 5 = sta : start of conversion. write only . 0: no effect 1: start conversion note: setting this bit automatically clears the eoc bit. if the bit is set again when a conversion is in progress, the present conversion is stopped and a new one will take place. th is bit is write only, any attempt to read it will show a logical zero. bit 4 = pds power down selection. 0: a/d converter is switched off 1: a/d converter is switched on bit 3 = adcr3 reserved , must be cleared. bit 2 = oscoff main oscillator off. 0: main oscillator enabled 1: main oscillator disabled note: this bit does not apply to the adc peripher - al but to the main clock system. refer to the clock system section. bits 1:0 = adcr[1:0] reserved , must be cleared. a/d converter data register (adr) address: 0d0h - read only reset value: xxxx xxxx (xxh) bits 7:0 = adr[7:0] : 8 bit a/d conversion result. table 14. adc register map and reset values mode description wait no effect on a/d converter. adc interrupts cause the device to exit from wait mode. stop a/d converter disabled. interrupt event event flag enable bit exit from wait exit from stop end of conver - sion eoc eai yes no 7 0 eai eoc sta pds adcr 3 osc off adcr 1 adcr 0 7 0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 address (hex.) register label 7 6 5 4 3 2 1 0 0d0h adr reset value adr7 0 adr6 0 adr5 0 adr4 0 adr3 0 adr2 0 adr1 0 adr0 0 0d1h adcr reset value eai 0 eoc 1 sta 0 pds 0 adcr3 0 oscoff 0 adcr1 0 adcr0 0 1
st6200c st6201c st6203c 52/100 doc id 4563 rev 5 9 instruction set 9.1 st6 architecture the st6 architecture has been designed for max - imum efficiency while keeping byte usage to a minimum; in short, to pr ovide byte-efficient pro - gramming. the st6 core has the ability to set or clear any register or ra m location bit in data space using a single instruction. furthermore, pro - grams can branch to a selected address depend - ing on the status of any bit in data space. 9.2 addressing modes the st6 has nine addressing modes, which are described in the follow ing paragraphs. three dif - ferent address spaces are available: program space, data space, and stack space. program space contains the instru ctions which are to be ex - ecuted, plus the data for immediate mode instruc - tions. data space contains the accumulator, the x, y, v and w registers, peripheral and input/output registers, the ram locations and data rom loca - tions (for storage of tables and constants). stack space contains six 12-bit ram cells used to stack the return addresses for subroutines and inter - rupts. immediate . in immediate addressing mode, the operand of the instruction follows the opcode loca - tion. as the operand is a rom byte, the immediate addressing mode is used to access constants which do not change during program execution (e.g., a constant used to initialize a loop counter). direct . in direct addressing mode, the address of the byte which is process ed by the instruction is stored in the location which follows the opcode. di - rect addressing allows the user to directly address the 256 bytes in data space memory with a single two-byte instruction. short direct . the core can address the four ram registers x, y, v, w (locations 80h, 81h, 82h, 83h) in short-direct addressing mode. in this case, the instruction is only one byte and the selection of the location to be processed is contained in the op - code. short direct addressing is a subset of direct addressing mode. (note that 80h and 81h are also indirect registers). extended . in extended addressing mode, the 12- bit address needed to define the instruction is ob - tained by concatenating the four least significant bits of the opcode with the byte following the op - code. the instructions (jp, call) which use ex - tended addressing mode are able to branch to any address in the 4 kbyte program space. extended addressing mode instructions are two bytes long. program counter relative . relative addressing mode is only used in conditional branch instruc - tions. the instruction is used to perform a test and, if the condition is true, a branch with a span of -15 to +16 locations next to the address of the relative instruction. if the condition is not true, the instruc - tion which follows the relative instruction is execut - ed. relative addressing mode instructions are one byte long. the opcode is obtained by adding the three most significant bits which characterize the test condition, one bit which determines whether it is a forward branch (when it is 0) or backward branch (when it is 1) and t he four least significant bits which give the span of the branch (0h to fh) which must be added or subtracted from the ad - dress of the relative instruction to obtain the branch destination address. bit direct . in bit direct addressing mode, the bit to be set or cleared is part of the opcode, and the byte following the opcode points to the address of the byte in which the specified bit must be set or cleared. thus, any bit in the 256 locations of data space memory can be set or cleared. bit test & branch . bit test and branch addressing mode is a combination of direct addressing and relative addressing. bit test and branch instruc - tions are three bytes long. the bit identification and the test condition are included in the opcode byte. the address of the byte to be tested is given in the next byte. the third byte is the jump dis - placement, which is in the range of -127 to +128. this displacement can be determined using a la - bel, which is converted by the assembler. indirect . in indirect addressing mode, the byte processed by the r egister-indirect instruction is at the address pointed to by the content of one of the indirect registers, x or y (80h, 81h). the indirect register is selected by bit 4 of the opcode. register indirect instructions are one byte long. inherent . in inherent addressing mode, all the in - formation necessary for executing the instruction is contained in the opcode. these instructions are one byte long. 1
st6200c st6201c st6203c doc id 4563 rev 5 53/100 9.3 instruction set the st6 offers a set of 40 basic instructions which, when combined with nine addressing modes, yield 244 usable opcodes. they can be di - vided into six different ty pes: load/store, arithme - tic/logic, conditional bran ch, control instructions, jump/call, and bit manipulation. the following par - agraphs describe the different types. all the instructions belonging to a given type are presented in individual tables. load & store . these instructions use one, two or three bytes depending on the addressing mode. for load, one operand is the accumulator and the other operand is obtained from data memory using one of the addressing modes. for load immediate, one operand can be any of the 256 data space bytes while the other is always immediate data. table 15. load & store instructions legend: x, y index registers, v, w short direct registers # immediate data (stored in rom memory) rr data space register affected * not affected instruction addressing mode bytes cycles flags z c ld a, x short direct 1 4 * ld a, y short direct 1 4 * ld a, v short direct 1 4 * ld a, w short direct 1 4 * ld x, a short direct 1 4 * ld y, a short direct 1 4 * ld v, a short direct 1 4 * ld w, a short direct 1 4 * ld a, rr direct 2 4 * ld rr, a direct 2 4 * ld a, (x) indirect 1 4 * ld a, (y) indirect 1 4 * ld (x), a indirect 1 4 * ld (y), a indirect 1 4 * ldi a, #n immediate 2 4 * ldi rr, #n immediate 3 4 * * 1
st6200c st6201c st6203c 54/100 doc id 4563 rev 5 instruction set (cont?d) arithmetic and logic . these instructions are used to perform arithmetic calculations and logic operations. in and, add, cp, sub instructions one operand is always the accumulator while, de - pending on the addressing mode, the other can be either a data space memory location or an imme - diate value. in clr, dec, inc instructions the op - erand can be any of the 256 data space address - es. in com, rlc, sla the operand is always the accumulator. table 16. arithmetic & logic instructions notes: x,y index registers v, w short direct registers affected # immediate data (stored in rom memory) * not affected rr data space register instruction addressing mode bytes cycles flags z c add a, (x) indirect 1 4 add a, (y) indirect 1 4 add a, rr direct 2 4 addi a, #n immediate 2 4 and a, (x) indirect 1 4 and a, (y) indirect 1 4 and a, rr direct 2 4 andi a, #n immediate 2 4 clr a short direct 2 4 clr r direct 3 4 * * com a inherent 1 4 cp a, (x) indirect 1 4 cp a, (y) indirect 1 4 cp a, rr direct 2 4 cpi a, #n immediate 2 4 dec x short direct 1 4 * dec y short direct 1 4 * dec v short direct 1 4 * dec w short direct 1 4 * dec a direct 2 4 * dec rr direct 2 4 * dec (x) indirect 1 4 * dec (y) indirect 1 4 * inc x short direct 1 4 * inc y short direct 1 4 * inc v short direct 1 4 * inc w short direct 1 4 * inc a direct 2 4 * inc rr direct 2 4 * inc (x) indirect 1 4 * inc (y) indirect 1 4 * rlc a inherent 1 4 sla a inherent 2 4 sub a, (x) indirect 1 4 sub a, (y) indirect 1 4 sub a, rr direct 2 4 subi a, #n immediate 2 4 1
st6200c st6201c st6203c doc id 4563 rev 5 55/100 instruction set (cont?d) conditional branch . branch instructions perform a branch in the program when the selected condi - tion is met. bit manipulation instructions . these instruc - tions can handle any bit in data space memory. one group either sets or clears. the other group (see conditional branch) pe rforms the bit test branch operations. control instructions . control instructions control microcontroller operati ons during program execu - tion. jump and call. these two instructions are used to perform long (12-bit) jumps or subroutine calls to any location in the whole program space. table 17. conditional branch instructions notes : b 3-bit address rr data space register e 5 bit signed displacement in the range -15 to +16 affected. the tested bit is shifted into carry. ee 8 bit signed displacement in the range -126 to +129 * not affected table 18. bit manipulation instructions notes: b 3-bit address * not affected rr data space register bit manipulation instructions should not be used on port data registers and any registers with read only and/or write only bits (see i/o port chapter) table 19. control instructions notes: 1. this instruction is deactivated and a wait is automatically exec uted instead of a stop if the watchdog function is selected. affected *not affected table 20. jump & call instructions notes: abc 12-bit address * not affected instruction branch if bytes cycles flags z c jrc e c = 1 1 2 * * jrnc e c = 0 1 2 * * jrz e z = 1 1 2 * * jrnz e z = 0 1 2 * * jrr b, rr, ee bit = 0 3 5 * jrs b, rr, ee bit = 1 3 5 * instruction addressing mode bytes cycles flags z c set b,rr bit direct 2 4 * * res b,rr bit direct 2 4 * * instruction addressing mode bytes cycles flags z c nop inherent 1 2 * * ret inherent 1 2 * * reti inherent 1 2 stop (1) inherent 1 2 * * wait inherent 1 2 * * instruction addressing mode bytes cycles flags z c call abc extended 2 4 * * jp abc extended 2 4 * * 1
st6200c st6201c st6203c 56/100 doc id 4563 rev 5 opcode map summary. the following table contains an opcode ma p for the instructions used by the st6 low 0 0000 1 0001 2 0010 3 0011 4 0100 5 0101 6 0110 7 0111 low hi hi 0 0000 2 jrnz 4 call 2 jrnc 5 jrr 2 jrz 2 jrc 4 ld 0 0000 e abc e b0,rr,ee e nop # e a,(x) 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind 1 0001 2 jrnz 4 call 2 jrnc 5 jrs 2 jrz 4 inc 2 jrc 4 ldi 1 0001 e abc e b0,rr,ee e x e a,nn 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc 2 imm 2 0010 2 jrnz 4 call 2 jrnc 5 jrr 2 jrz 2 jrc 4 cp 2 0010 e abc e b4,rr,ee e # e a,(x) 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind 3 0011 2 jrnz 4 call 2 jrnc 5 jrs 2 jrz 4 ld 2 jrc 4 cpi 3 0011 e abc e b4,rr,ee e a,x e a,nn 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc 2 imm 4 0100 2 jrnz 4 call 2 jrnc 5 jrr 2 jrz 2 jrc 4 add 4 0100 e abc e b2,rr,ee e # e a,(x) 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind 5 0101 2 jrnz 4 call 2 jrnc 5 jrs 2 jrz 4 inc 2 jrc 4 addi 5 0101 e abc e b2,rr,ee e y e a,nn 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc 2 imm 6 0110 2 jrnz 4 call 2 jrnc 5 jrr 2 jrz 2 jrc 4 inc 6 0110 e abc e b6,rr,ee e # e (x) 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind 7 0111 2 jrnz 4 call 2 jrnc 5 jrs 2 jrz 4 ld 2 jrc 7 0111 e abc e b6,rr,ee e a,y e # 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc 8 1000 2 jrnz 4 call 2 jrnc 5 jrr 2 jrz 2 jrc 4 ld 8 1000 e abc e b1,rr,ee e # e (x),a 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind 9 1001 2 jrnz 4 call 2 jrnc 5 jrs 2 jrz 4 inc 2 jrc 9 1001 e abc e b1,rr,ee e v e # 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc a 1010 2 jrnz 4 call 2 jrnc 5 jrr 2 jrz 2 jrc 4 and a 1010 e abc e b5,rr,ee e # e a,(x) 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind b 1011 2 jrnz 4 call 2 jrnc 5 jrs 2 jrz 4 ld 2 jrc 4 andi b 1011 e abc e b5,rr,ee e a,v e a,nn 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc 2 imm c 1100 2 jrnz 4 call 2 jrnc 5 jrr 2 jrz 2 jrc 4 sub c 1100 e abc e b3,rr,ee e # e a,(x) 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind d 1101 2 jrnz 4 call 2 jrnc 5 jrs 2 jrz 4 inc 2 jrc 4 subi d 1101 e abc e b3,rr,ee e w e a,nn 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc 2 imm e 1110 2 jrnz 4 call 2 jrnc 5 jrr 2 jrz 2 jrc 4 dec e 1110 e abc e b7,rr,ee e # e (x) 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 prc 1 ind f 1111 2 jrnz 4 call 2 jrnc 5 jrs 2 jrz 4 ld 2 jrc f 1111 e abc e b7,rr,ee e a,w e # 1 pcr 2 ext 1 pcr 3 bt 1 pcr 1 sd 1 prc abbreviations for addressing modes: legend: dir direct # indicates illegal instructions sd short direct e 5-bit displacement imm immediate b 3-bit address inh inherent rr 1-byte data space address ext extended nn 1-byte immediate data b.d bit direct abc 12-bit address bt bit test ee 8-bit displacement pcr program counter relative ind indirect 2 jrc e 1prc mnemonic addressing mode bytes cycles operands 1
st6200c st6201c st6203c doc id 4563 rev 5 57/100 opcode map summary (continued) low 8 1000 9 1001 a 1010 b 1011 c 1100 d 1101 e 1110 f 1111 low hi hi 0 0000 2 jrnz 4 jp 2 jrnc 4 res 2 jrz 4 ldi 2 jrc 4 ld 0 0000 e abc e b0,rr e rr,nn e a,(y) 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 3 imm 1 prc 1 ind 1 0001 2 jrnz 4 jp 2 jrnc 4 set 2 jrz 4 dec 2 jrc 4 ld 1 0001 e abc e b0,rr e x e a,rr 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 prc 2 dir 2 0010 2 jrnz 4 jp 2 jrnc 4 res 2 jrz 4 com 2 jrc 4 cp 2 0010 e abc e b4,rr e a e a,(y) 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 prc 1 ind 3 0011 2 jrnz 4 jp 2 jrnc 4 set 2 jrz 4 ld 2 jrc 4 cp 3 0011 e abc e b4,rr e x,a e a,rr 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 prc 2 dir 4 0100 2 jrnz 4 jp 2 jrnc 4 res 2 jrz 2 reti 2 jrc 4 add 4 0100 e abc e b2,rr e e a,(y) 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 inh 1 prc 1 ind 5 0101 2 jrnz 4 jp 2 jrnc 4 set 2 jrz 4 dec 2 jrc 4 add 5 0101 e abc e b2,rr e y e a,rr 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 prc 2 dir 6 0110 2 jrnz 4 jp 2 jrnc 4 res 2 jrz 2 stop 2 jrc 4 inc 6 0110 e abc e b6,rr e e (y) 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 inh 1 prc 1 ind 7 0111 2 jrnz 4 jp 2 jrnc 4 set 2 jrz 4 ld 2 jrc 4 inc 7 0111 e abc e b6,rr e y,a e rr 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 prc 2 dir 8 1000 2 jrnz 4 jp 2 jrnc 4 res 2 jrz 2 jrc 4 ld 8 1000 e abc e b1,rr e # e (y),a 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 prc 1 ind 9 1001 2 jrnz 4 jp 2 jrnc 4 set 2 jrz 4 dec 2 jrc 4 ld 9 1001 e abc e b1,rr e v e rr,a 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 prc 2 dir a 1010 2 jrnz 4 jp 2 jrnc 4 res 2 jrz 4 rcl 2 jrc 4 and a 1010 e abc e b5,rr e a e a,(y) 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 inh 1 prc 1 ind b 1011 2 jrnz 4 jp 2 jrnc 4 set 2 jrz 4 ld 2 jrc 4 and b 1011 e abc e b5,rr e v,a e a,rr 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 prc 2 dir c 1100 2 jrnz 4 jp 2 jrnc 4 res 2 jrz 2 ret 2 jrc 4 sub c 1100 e abc e b3,rr e e a,(y) 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 inh 1 prc 1 ind d 1101 2 jrnz 4 jp 2 jrnc 4 set 2 jrz 4 dec 2 jrc 4 sub d 1101 e abc e b3,rr e w e a,rr 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 prc 2 dir e 1110 2 jrnz 4 jp 2 jrnc 4 res 2 jrz 2 wait 2 jrc 4 dec e 1110 e abc e b7,rr e e (y) 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 inh 1 prc 1 ind f 1111 2 jrnz 4 jp 2 jrnc 4 set 2 jrz 4 ld 2 jrc 4 dec f 1111 e abc e b7,rr e w,a e rr 1 pcr 2 ext 1 pcr 2 b.d 1 pcr 1 sd 1 prc 2 dir abbreviations for addressing modes: legend: dir direct # indicates illegal instructions sd short direct e 5-bit displacement imm immediate b 3-bit address inh inherent rr 1-byte data space address ext extended nn 1-byte immediate data b.d bit direct abc 12-bit address bt bit test ee 8-bit displacement pcr program counter relative ind indirect 2 jrc e 1prc mnemonic addressing mode bytes cycles operands 1
st6200c st6201c st6203c 58/100 doc id 4563 rev 5 10 electrical characteristics 10.1 parameter conditions unless otherwise specif ied, all voltages are re - ferred to v ss . 10.1.1 minimum and maximum values unless otherwise specif ied the minimum and max - imum values are guarant eed in the worst condi - tions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at t a =25c and t a =t a max (given by the selected temperature range). data based on characterization results, design simulation and/or technol ogy characteristics are indicated in the table footnotes and are not tested in production. based on c haracterization, the min - imum and maximum values refer to sample tests and represent the mean valu e plus or minus three times the standard deviation (mean3 ). 10.1.2 typical values unless otherwise specified, typical data are based on t a =25c, v dd =5v (for the 4.5v v dd 6.0v volt - age range) and v dd =3.3v (for the 3v v dd 3.6v voltage range). they ar e given only as design guidelines and are not tested. 10.1.3 typical curves unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 10.1.4 loading capacitor the loading conditions used for pin parameter measurement is shown in figure 30 . figure 30. pin loading conditions 10.1.5 pin input voltage the input voltage measurement on a pin of the de - vice is described in figure 31 . figure 31. pin input voltage c l st6 pin v in st6 pin 1
st6200c st6201c st6203c doc id 4563 rev 5 59/100 10.2 absolute maximum ratings stresses above those listed as ?absolute maxi - mum ratings? may cause permanent damage to the device. this is a stress rating only and func - tional operation of the device under these condi - tions is not implied. exposure to maximum rating conditions for extended peri ods may affect device reliability. 10.2.1 voltage characteristics 10.2.2 current characteristics 10.2.3 thermal characteristics notes: 1. directly connecting the reset and i/o pins to v dd or v ss could damage the device if an unintentional internal reset is generated or an unexpected change of the i/o configuratio n occurs (for example, due to a corrupted program coun - ter). to guarantee safe operation, this connection has to be done through a pull-up or pull-down resistor (typical: 4.7k for reset , 10k for i/os). unused i/o pins must be tied in the same way to v dd or v ss according to their reset con - figuration. 2. when the current limitation is not possible, the v in absolute maximum rating must be respected, otherwise refer to i inj(pin) specification. a positive injection is induced by v in >v dd while a negative injection is induced by v in st6200c st6201c st6203c 60/100 doc id 4563 rev 5 10.3 operating conditions 10.3.1 general operating conditions notes: 1. an oscillator frequency above 1.2mhz is recommended for reliable a/d results. 2. operating conditions with t a =-40 to +125c. figure 32. f osc maximum operating frequency versus v dd supply voltage for otp & rom devices symbol parameter conditions min max unit v dd supply voltage see figure 32 3.0 6 v f osc oscillator frequency v dd =3.0v, 1 & 6 suffix 0 1) 4 mhz v dd =3.0v, 3 suffix 0 1) 4 v dd =3.6v, 1 & 6suffix 0 1) 8 v dd =3.6v, 3 suffix 0 1) 4 v dd operating supply voltage f osc =4mhz, 1 & 6 suffix 3.0 6.0 v f osc =4mhz, 3 suffix 3.0 6.0 f osc =8mhz, 1 & 6 suffix 3.6 6.0 f osc =8mhz, 3 suffix 4.5 6.0 t a ambient temperature range 1 suffix version 0 70 c 6 suffix version -40 85 3 suffix version -40 125 1 2.5 3.644.555.56 8 7 6 5 4 3 2 supply 3 f osg f osg min f osc [mhz] functionality not guaranteed in this area 3 voltage (v dd ) 2 1 1. in this area, operation is guaranteed at the quartz crystal frequency. 2. when the osg is disabled, operation in this area is guaranteed at the crystal frequency. when the 3. when the osg is disabled, operation in this ar ea is guaranteed at the quartz crystal frequency. when osg is enabled, operation in this area is guaranteed at a frequency of at least f osg min. the osg is enabled, access to th is area is prevented. the inte rnal frequency is kept at f osg . 1 & 6 suffix version 3 suffix version 1
st6200c st6201c st6203c doc id 4563 rev 5 61/100 operating conditions (cont?d) 10.3.2 operating conditions with low voltage detector (lvd) subject to general operat ing conditions for v dd , f osc , and t a . notes: 1. lvd typical data are based on t a =25c. they are given only as design guidelines and are not tested. 2. the minimum v dd rise time rate is needed to insure a correct device power-on and lvd reset. not tested in production. 3. data based on characterization results, not tested in production. figure 33. lvd threshold versus v dd and f osc 3) figure 34. typical lvd thresholds versus temperature for otp devices figure 35. typical lvd thresholds vs. temperature for rom devices symbol parameter conditions min typ 1) max unit v it+ reset release threshold (v dd rise) 3.9 4.1 4.3 v v it- reset generation threshold (v dd fall) 3.6 3.8 4 v hys lvd voltage threshold hysteresis v it+ -v it- 50 300 700 mv vt por v dd rise time rate 2) mv/s t g(vdd) filtered glitch delay on v dd 3) not detected by the lvd 30 ns f osc [mhz] supply 8 4 0 2.5 3 3.5 4 4.5 5 5.5 functional area reset functionality not guaranteed in this area v it- 3.6 device under in this area 6 voltage [v] -40c 25c 95c 125c t [c] 3.6 3.8 4 4.2 thresholds [v] vdd up vdd down v it+ v it- -40c 25c 95c 125c t [c] 3.6 3.8 4 4.2 thresholds [v] vdd up vdd down v it+ v it- 1
st6200c st6201c st6203c 62/100 doc id 4563 rev 5 10.4 supply current characteristics the following current c onsumption specified for the st6 functional operating modes over tempera - ture range does not take into account the clock source current consumption. to get the total de - vice consumption, the two current values must be added (except for stop mode for which the clock is stopped). 10.4.1 run modes notes: 1. typical data are based on t a =25c, v dd =5v (4.5v v dd 6.0v range) and v dd =3.3v (3v v dd 3.6v range). 2. data based on characterization results, tested in production at v dd max. and f osc max. 3. cpu running with memory access, all i/o pins in input with pull-up mode (no load), all peripherals in reset state; clock input (osc in ) driven by external square wave, osg and lvd disabled, option bytes not programmed. figure 36. typical i dd in run vs. f cpu figure 37. typical i dd in run vs. temperature (v dd = 5v) symbol parameter conditions typ 1) max 2) unit i dd supply current in run mode 3) (see figure 36 & figure 37 ) 4.5v v dd 6.0v f osc =32khz f osc =1mhz f osc =2mhz f osc =4mhz f osc =8mhz 0.5 1.3 1.6 2.2 3.3 0.7 1.7 2.4 3.3 4.8 ma supply current in run mode 3) (see figure 36 & figure 37 ) 3v v dd 3.6v f osc =32khz f osc =1mhz f osc =2mhz f osc =4mhz f osc =8mhz 0.3 0.6 0.9 1.0 1.8 0.4 0.8 1.2 1.5 2.3 34 56 vdd [v] 0 1 2 3 4 5 idd [ma] 8mhz 4mhz 2mhz 1mhz 32khz -40 25 95 125 t[c] 0 0.5 1 1.5 2 2.5 3 3.5 idd [ma] 8mhz 4mhz 2mhz 1mhz 32khz 1
st6200c st6201c st6203c doc id 4563 rev 5 63/100 supply current characteristics (cont?d) 10.4.2 wait modes notes: 1. typical data are based on t a =25c, v dd =5v (4.5v v dd 6.0v range) and v dd =3.3v (3v v dd 3.6v range). 2. data based on characterization results, tested in production at v dd max. and f osc max. 3. all i/o pins in input with pull-up mode (no load), all peripherals in reset state; clock input (osc in ) driven by external square wave, osg and lvd disabled. symbol parameter conditions typ 1) max 2) unit i dd supply current in wait mode 3) option bytes not programmed (see figure 38 ) 4.5v v dd 6.0v otp devices f osc =32khz f osc =1mhz f osc =2mhz f osc =4mhz f osc =8mhz 330 350 370 410 480 550 600 650 700 800 a supply current in wait mode 3) option bytes programmed to 00h (see figure 39 ) f osc =32khz f osc =1mhz f osc =2mhz f osc =4mhz f osc =8mhz 18 26 41 57 70 60 80 120 180 200 supply current in wait mode 3) (see figure 40 ) rom devices f osc =32khz f osc =1mhz f osc =2mhz f osc =4mhz f osc =8mhz 190 210 240 280 350 300 350 400 500 600 supply current in wait mode 3) option bytes not programmed (see figure 38 ) 3v v dd 3.6v otp devices f osc =32khz f osc =1mhz f osc =2mhz f osc =4mhz f osc =8mhz 80 90 100 120 150 120 140 150 200 250 supply current in wait mode 3) option bytes programmed to 00h (see figure 39 ) f osc =32khz f osc =1mhz f osc =2mhz f osc =4mhz f osc =8mhz 5 8 16 18 20 30 40 50 60 100 supply current in wait mode 3) option bytes not programmed (see figure 40 ) rom devices f osc =32khz f osc =1mhz f osc =2mhz f osc =4mhz f osc =8mhz 60 65 80 100 130 100 110 120 150 210 1
st6200c st6201c st6203c 64/100 doc id 4563 rev 5 supply current characteristics (cont?d) figure 38. typical i dd in wait vs f cpu and temperature for otp devices with option bytes not programmed figure 39. typical i dd in wait vs f cpu and temperature for otp devices with option bytes programmed to 00h 34 56 vdd [v] 0 100 200 300 400 500 600 700 800 idd [a] 8mhz 4mhz 2mhz 1m 32khz -40 25 95 125 t[c] 200 300 400 500 600 700 idd [a] 8mhz 4mhz 2mhz 1mhz 32khz 34 56 vdd [v] 0 20 40 60 80 100 120 idd [a] 8mhz 4mhz 2mhz 1m 32khz -20 25 95 t[c] 10 20 30 40 50 60 70 80 90 idd [a] 8mhz 4mhz 2mhz 1mhz 32khz 1
st6200c st6201c st6203c doc id 4563 rev 5 65/100 supply current characteristics (cont?d) figure 40. typical i dd in wait vs f cpu and temperature for rom devices 34 56 vdd [v] 0 100 200 300 400 500 600 idd [a] 8mhz 4mhz 2mhz 1m 32khz -20 25 95 125 t[c] 100 150 200 250 300 350 400 450 idd [a] 8mhz 4mhz 2mhz 1mhz 32khz 1
st6200c st6201c st6203c 66/100 doc id 4563 rev 5 supply current characteristics (cont?d) 10.4.3 stop mode notes: 1. typical data are based on v dd =5.0v at t a =25c. 2. all i/o pins in input with pull-up mode (no load), all peripherals in reset state, osg and lvd disabled, option bytes programmed to 00h. data based on characterization results, tested in production at v dd max. and f cpu max. 3. maximum stop consumption for -40c st6200c st6201c st6203c doc id 4563 rev 5 67/100 supply current characteristics (cont?d) 10.4.4 supply and clock system the previous current c onsumption specified for the st6 functional operating modes over tempera - ture range does not take into account the clock source current consumption. to get the total de - vice consumption, the two current values must be added (except for stop mode). 10.4.5 on-chip peripherals notes: 1. typical data are based on t a =25c. 2. data based on characterization results, not tested in production. 3. data based on a differential i dd measurement between reset configuration (osg and lfao disabled) and lfao run - ning (also includes the osg stand alone consumption). 4. data based on a differential i dd measurement between reset configuration with osg disabled and osg enabled. 5. data based on a differential i dd measurement between reset configuration with lvd disabled and lvd enabled. 6. data based on a differential i dd measurement between reset configurati on (timer disabled) and timer running. 7. data based on a differential i dd measurement between reset configurat ion and continuous a/d conversions. symbol parameter conditions typ 1) max 2) unit i dd(ck) supply current of rc oscillator f osc =32 khz, f osc =1 mhz f osc =2 mhz f osc =4 mhz f osc =8 mhz v dd = 5.0 v 230 260 340 480 a f osc =32 khz, f osc =1 mhz f osc =2 mhz f osc =4 mhz f osc =8 mhz v dd = 3.3 v 80 110 180 320 supply current of resonator oscillator f osc =32 khz, f osc =1 mhz f osc =2 mhz f osc =4 mhz f osc =8mhz v dd = 5.0 v 900 280 240 140 40 f osc =32 khz, f osc =1 mhz f osc =2 mhz f osc =4 mhz f osc =8 mhz v dd = 3.3 v 120 70 50 20 10 i dd(lfao) lfao supply current 3) v dd = 5.0 v 102 i dd(osg) osg supply current 4) v dd = 5.0 v 40 i dd(lvd) lvd supply current 5) v dd = 5.0 v 170 symbol parameter conditions typ 1) unit i dd(tim) 8-bit timer supply current 6) f osc =8 mhz v dd = 5.0 v 170 a v dd = 3.3 v 100 i dd(adc) adc supply current when converting 7) f osc =8 mhz v dd = 5.0 v 80 v dd = 3.3 v 50 1
st6200c st6201c st6203c 68/100 doc id 4563 rev 5 10.5 clock and timing characteristics subject to general operat ing conditions for v dd , f osc , and t a . 10.5.1 general timings 10.5.2 external clock source notes: 1. data based on typical application software. 2. time measured between interrupt event and interrupt vector fetch. t c(inst) is the number of t cpu cycles needed to finish the current instruction execution. figure 43. typical application with an external clock source symbol parameter conditions min typ 1) max unit t c(inst) instruction cycle time 2 4 5 t cpu f cpu =8 mhz 3.25 6.5 8.125 s t v(it) interrupt reaction time 2) t v(it) = t c(inst) + 6 6 11 t cpu f cpu =8 mhz 9.75 17.875 s symbol parameter conditions min typ max unit v oscinh osc in input pin high level voltage see figure 43 0.7xv dd v dd v v oscinl osc in input pin low level voltage v ss 0.3xv dd i l oscx input leakage current v ss v in v dd 2 a osc in osc out f osc external st62xx clock source v oscinl v oscinh i l 90% 10% not connected 1
st6200c st6201c st6203c doc id 4563 rev 5 69/100 clock and timing characteristics (cont?d) 10.5.3 crystal and ceramic resonator oscillators the st6 internal clock can be supplied with sever - al different crystal/cera mic resonator oscillators. only parallel resonant crys tals can be used. all the information given in this paragraph are based on characterization results with specified typical ex - ternal components. refer to the crystal/ceramic resonator manufacturer for more details (frequen - cy, package, accuracy...). notes: 1. resonator characteristics given by t he crystal/ceramic resonator manufacturer. 2. t su(osc) is the typical oscillator start-up time measured between v dd =2.8v and the fetch of the first instruction (with a quick v dd ramp-up from 0 to 5v (<50 s). 3. the oscillator selection can be optimized in terms of supply current using an high quality resonator with small r s value. refer to crystal/ceramic resonator manufacturer for more details. figure 44. typical application with a crystal or ceramic resonator symbol parameter conditions typ unit r f feedback resistor 3 m c l1 c l2 recommended load capacit ances versus equiva - lent crystal or ceramic resonator frequency f osc =32 khz, f osc =1 mhz f osc =2 mhz f osc =4 mhz f osc =8 mhz 120 47 33 33 22 pf oscillator typical crystal or ceramic resonators c l1 [ pf ] c l2 [ pf ] t su(osc) [ ms ] 1) reference freq. characteristic 1) ceramic murata csb455e 455khz f osc =[0.5khz tolerance ,0.3% ta , 0.5% aging ] 220 220 csb1000j 1mhz f osc =[0.5khz tolerance ,0.3% ta , 0.5% aging ] 100 100 cstcc2.00mg0h6 2mhz f osc =[0.5% tolerance ,0.5% ta , 0.3% aging ] 47 47 cstcc4.00mg0h6 4mhz f osc =[0.5% tolerance ,0.3% ta , 0.3% aging ] 47 47 cstcc8.00mg 8mhz f osc =[0.5% tolerance ,0.3% ta , 0.3% aging ] 15 15 osc out osc in c l1 c l2 r f st62xx resonator v dd f osc 1
st6200c st6201c st6203c 70/100 doc id 4563 rev 5 clock and timing characteristics (cont?d) 10.5.4 rc oscillator the st6 internal clock can be supplied with an external rc oscillator. depending on the r net value, the accuracy of the frequency is about 20%, so it may not be suitable for some applications. notes: 1. data based on characterization results, not tested in production. these measurements were done with the oscin pin unconnected (only soldered on the pcb). 2. r net must have a positive temperature coefficient (ppm /c), carbon resistors should therefore not be used. figure 45. typical application with rc oscillator symbol parameter conditions min typ max unit f osc rc oscillator frequency 1) 4.5v v dd 6.0v r net =22 k r net =47 k r net =100 k r net =220 k r net =470 k 7.2 5.1 3.2 1.8 0.9 8.6 5.7 3.4 1.9 0.95 10 6.5 3.8 2 1.1 mhz 3v v dd 3.6v r net =22 k r net =47 k r net =100 k r net =220 k r net =470 k 3.7 2.8 1.8 1 0.5 4.3 3 1.9 1.1 0.55 4.9 3.3 2 1.2 0.6 r net rc oscillator external resistor 2) see figure 46 & figure 47 22 870 k osc in osc out r net external rc c ex ~9pf discharge st62xx v dd v dd f osc v dd nc mirror current 1
st6200c st6201c st6203c doc id 4563 rev 5 71/100 clock and timing characteristics (cont?d) figure 46. typical rc oscillator frequency vs. v dd figure 47. typical rc oscillator frequency vs. temperature (v dd = 5v) 10.5.5 oscillator safeguard (osg) and low frequency auxiliary oscillator (lfao) figure 48. typical lfao frequencies note: 1. data based on characterization results. 34 56 vdd [v] 0 2 4 6 8 10 12 fosc [mhz] rnet=22kohm rnet=47kohm rnet=100kohm rnet=220kohm rnet=470kohm -40 25 95 125 ta [c] 0 2 4 6 8 10 fosc [mhz] rnet=22kohm rnet=47kohm rnet=100kohm rnet=220kohm rnet=470kohm symbol parameter conditions min typ max unit f lfao low frequency auxiliary oscillator frequency 1) t a = 25 c, v dd = 5.0 v 200 350 800 khz t a = 25 c, v dd = 3.3 v 86 150 340 f osg internal frequency with osg ena - bled t a = 25 c, v dd = 4.5 v 4 mhz t a = 25 c, v dd = 3.3 v 2 34 5 6 vdd [v] 0 100 200 300 400 500 600 fosc [khz] ta=-40c ta=25c ta=125c 1
st6200c st6201c st6203c 72/100 doc id 4563 rev 5 10.6 memory characteristics subject to general operat ing conditions for v dd , f osc , and t a unless otherwise specified. 10.6.1 ram and hardware registers 10.6.2 eprom program memory figure 49. eprom retention time vs. temperature notes: 1. minimum v dd supply voltage without losing data stored in ram (in stop mode or under reset) or in hardware reg - isters (only in stop mode). guaranteed by construction, not tested in production. 2. data based on reliability test results and monitored in pr oduction. for otp devices, data retention and programmability must be guaranteed by a screening procedure. refer to application note an886. 3. the data retention time increases when the t a decreases, see figure 49 . symbol parameter conditions min typ max unit v rm data retention 1) 0.7 v symbol parameter conditions min typ max unit t ret data retention 2) t a =+55c 3) 10 years -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 temperature [c] 0.1 1 10 100 1000 10000 100000 retention time [years] 1
st6200c st6201c st6203c doc id 4563 rev 5 73/100 10.7 emc characteristics susceptibility tests are performed on a sample ba - sis during product characterization. 10.7.1 functional ems (electro magnetic susceptibility) based on a simple running application on the product (toggling 2 leds through i/o ports), the product is stressed by tw o electro magnetic events until a failure occurs (indicated by the leds). esd : electro-static discharge (positive and negative) is applied on all pins of the device until a functional disturbance occurs. this test conforms with the iec 1000-4-2 standard. ftb : a burst of fast transient voltage (positive and negative) is applied to v dd and v ss through a 100pf capacitor, until a functional disturbance occurs. this test conforms with the iec 1000-4- 4 standard. a device reset allows normal operations to be re - sumed. notes: 1. data based on characterization results, not tested in production. 2. the suggested 10 f and 0.1 f decoupling capacitors on the power supp ly lines are proposed as a good price vs. emc performance tradeoff. they have to be put as close as possible to the devic e power supply pins. other emc rec - ommendations are given in other sections (i/os, reset, oscx pin characteristics). figure 50. emc recommended star network power supply connection 2) symbol parameter conditions neg 1) pos 1) unit v fesd voltage limits to be applied on any i/o pin to induce a functional disturbance v dd = 5v, t a = +25c, f osc = 8mhz conforms to iec 1000-4-2 -2 2 kv v fftb fast transient voltage burst limits to be ap - plied through 100pf on v dd and v dd pins to induce a functional disturbance v dd = 5v, t a = +25c, f osc = 8mhz conforms to iec 1000-4-4 -2.5 3 v dd v ss 0.1 f 10 f v dd st62xx power supply source st6 digital noise filtering (close to the mcu) 1
st6200c st6201c st6203c 74/100 doc id 4563 rev 5 emc characteristics (cont?d) 10.7.2 absolute electrical sensitivity based on three different tests (esd, lu and dlu) using specific measurem ent methods, the product is stressed in order to determine its performance in terms of electrical sensit ivity. for more details, re - fer to the an1181 application note. 10.7.2.1 electro-static discharge (esd) electro-static discharges (3 positive then 3 nega - tive pulses separated by 1 second) are applied to the pins of each sample according to each pin combination. the sample size depends of the number of supply pins of the device (3 parts*(n+1) supply pin). two models are usually simulated: human body model and machine model. this test conforms to the jesd22-a114a/a115a standard. see figure 51 and the following test sequences. human body model test sequence ? c l is loaded through s1 by the hv pulse gener - ator. ? s1 switches position from generator to r. ? a discharge from c l through r (body resistance) to the st6 occurs. ? s2 must be closed 10 to 100ms after the pulse delivery period to ensure the st6 is not left in charge state. s2 must be opened at least 10ms prior to the delivery of the next pulse. machine model test sequence ? c l is loaded through s1 by the hv pulse gener - ator. ? s1 switches position from generator to st6. ? a discharge from c l to the st6 occurs. ? s2 must be closed 10 to 100ms after the pulse delivery period to ensure the st6 is not left in charge state. s2 must be opened at least 10ms prior to the delivery of the next pulse. ? r (machine resistance), in series with s2, en - sures a slow discharge of the st6. absolute maximum ratings notes: 1. data based on characterization results, not tested in production. figure 51. typical equivalent esd circuits symbol ratings conditions maximum value 1) unit v esd(hbm) electro-static discharge voltage (human body model) t a = +25c 2000 v v esd(mm) electro-static discharge voltage (machine model) t a = +25c 200 st6 s2 r=1500 s1 high voltage c l = 100pf pulse generator st6 s2 high voltage c l = 200pf pulse generator r=10k~10m s1 human body model machine model 1
st6200c st6201c st6203c doc id 4563 rev 5 75/100 emc characteristics (cont?d) 10.7.2.2 static and dynamic latch-up lu : 3 complementary static tests are required on 10 parts to assess the latch-up performance. a supply overvoltage ( applied to each power supply pin), a current injection (applied to each input, output and configurable i/o pin) and a power supply switch sequence are performed on each sample. this test conforms to the eia/ jesd 78 ic latch-up standard. for more details, refer to the an1181 application note. dlu : electro-static disc harges (one positive then one negative test) are applied to each pin of 3 samples when the micro is running to assess the latch-up performance in dynamic mode. power supplies are set to the typical values, the oscillator is connected as near as possible to the pins of the micro and the component is put in reset mode. this test conforms to the iec1000-4-2 and saej1752/3 standards and is described in figure 52 . for more details, refer to the an1181 application note. electrical sensitivities notes: 1. class description: a class is an stmicroelectronics internal specification. all its limits are higher than the jedec spec - ifications, that means when a device belongs to class a it exceeds the jedec standard. b class strictly covers all the jedec criteria (international standard). 2. schaffner nsg435 with a pointed test finger. figure 52. simplified diagram of the esd generator for dlu symbol parameter conditions class 1) lu static latch-up class t a = +25c t a = +85c a a dlu dynamic latch-up class v dd = 5v, f osc = 4mhz, t a = +25c a r ch =50m r d =330 c s = 150pf esd hv relay discharge tip discharge return connection generator 2) st6 v dd v ss 1
st6200c st6201c st6203c 76/100 doc id 4563 rev 5 emc characteristics (cont?d) 10.7.3 esd pin protection strategy to protect an integrated circuit against electro- static discharge the stress must be controlled to prevent degradation or destruction of the circuit el - ements. the stress generally affects the circuit el - ements which are connected to the pads but can also affect the internal devices when the supply pads receive the stress. the elements to be pro - tected must not receive excessive current, voltage or heating within their structure. an esd network combines the different input and output esd protections. this network works, by al - lowing safe discharge paths for the pins subjected to esd stress. two critical esd stress cases are presented in figure 53 and figure 54 for standard pins. standard pin protection to protect the output structure the following ele - ments are added: ? a diode to v dd (3a) and a diode from v ss (3b) ? a protection device between v dd and v ss (4) to protect the input structure the following ele - ments are added: ? a resistor in series with the pad (1) ? a diode to v dd (2a) and a diode from v ss (2b) ? a protection device between v dd and v ss (4) figure 53. positive stress on a standard pad vs. v ss figure 54. negative stress on a standard pad vs. v dd in v dd v ss (1) (2a) (2b) (4) out v dd v ss (3a) (3b) main path path to avoid in v dd v ss (1) (2a) (2b) (4) out v dd v ss (3a) (3b) main path 1
st6200c st6201c st6203c doc id 4563 rev 5 77/100 10.8 i/o port pin characteristics 10.8.1 general characteristics subject to general operat ing conditions for v dd , f osc , and t a unless otherwise specified. figure 55. typical r pu vs. v dd with v in = v ss notes: 1. unless otherwise specified, typical data are based on t a =25c and v dd =5v. 2. data based on characterization results, not tested in production. 3. hysteresis voltage between schmitt trigger switching le vels. based on characterization results, not tested. 4. the r pu pull-up equivalent resistor is based on a resistive transis tor. this data is based on characterization results, not tested in production. 5. data based on characterization results, not tested in production. 6. to generate an external interrupt, a minimum pulse width has to be applied on an i/o port pin configured as an external interrupt source. figure 56. two typical applications with unused i/o pin symbol parameter conditions min typ 1) max unit v il input low level voltage 2) 0.3xv dd v v ih input high level voltage 2) 0.7xv dd v hys schmitt trigger voltage hysteresis 3) v dd =5v 200 400 mv v dd =3.3v 200 400 i l input leakage current v ss v in v dd (no pull-up configured) 0.1 1 a r pu weak pull-up equivalent resistor 4) v in = v ss v dd =5v 40 110 350 k v dd =3.3v 80 230 700 c in i/o input pin capacitance 5 10 pf c out i/o output pin capacitance 5 10 pf t f(io)out output high to low level fall time 5) c l =50pf between 10% and 90% 30 ns t r(io)out output low to high level rise time 5) 35 t w(it)in external interrupt pulse time 6) 1 t cpu 34 56 vdd [v] 50 100 150 200 250 300 350 rpu [khom] ta=-40c ta=25c ta=95c ta=125c 10k unused i/o port st62xx 10k unused i/o port st62xx v dd 1
st6200c st6201c st6203c 78/100 doc id 4563 rev 5 i/o port pin characteristics (cont?d) 10.8.2 output driving current subject to general operat ing conditions for v dd , f osc , and t a unless otherwise specified. notes: 1. the i io current sunk must always respect the absolute maximum rating specified in section 10.2.2 and the sum of i io (i/o ports and control pins) must not exceed i vss . 2. the i io current source must always respect the absolute maximum rating specified in section 10.2.2 and the sum of i io (i/o ports and control pins) must not exceed i vdd . true open drain i/o pins does not have v oh . figure 57. typical v ol at v dd = 5v (standard) figure 58. typical v ol at v dd = 5v (high-sink) symbol parameter conditions min max unit v ol 1) output low level voltage for a standard i/o pin (see figure 57 and figure 60 ) v dd =5v i io =+10a, t a 125c 0.1 v i io =+3ma, t a 125c 0.8 i io =+5ma, t a 85c 0.8 i io =+10ma, t a 85c 1.2 output low level voltage for a high sink i/o pin (see figure 58 and figure 61 ) i io =+10a, t a 125c 0.1 i io =+7ma, t a 125c 0.8 i io =+10ma, t a 85c 0.8 i io =+15ma, t a 125c 1.3 i io =+20ma, t a 85c 1.3 i io =+30ma, t a 85c 2 v oh 2) output high level voltage for an i/o pin (see figure 59 and figure 62 ) i io =-10 a, t a 125c v dd -0.1 i io =-3ma, t a 125c v dd -1.5 i io =-5ma, t a 85c v dd -1.5 024 6810 iio [ma] 0 200 400 600 800 1000 vol [mv] at vdd=5v ta=-40c ta=25c ta=95c ta=125c 04 8121620 iio [ma] 0 0.2 0.4 0.6 0.8 1 vol [v] at vdd=5v ta=-40c ta=25c ta=95c ta=125c 1
st6200c st6201c st6203c doc id 4563 rev 5 79/100 i/o port pin characteristics (cont?d) figure 59. typical v oh at v dd = 5v figure 60. typical v ol vs v dd (standard i/os) figure 61. typical v ol vs v dd (high-sink i/os) -8 -6 -4 -2 0 iio [ma] 3.5 4 4.5 5 voh [v] at vdd=5v ta=-40c ta=25c ta=95c ta=125c 3456 vdd [v] 150 200 250 300 350 vol [mv] at iio=2ma ta=-40c ta=25c ta=95c ta=125c 3456 vdd [v] 300 400 500 600 700 vol [mv] at iio=5ma ta=-40c ta=25c ta=95c ta=125c 3456 vdd [v] 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 vol [v] at iio=8ma ta=-40c ta=25c ta=95c ta=125c 3456 vdd [v] 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 vol [v] at iio=20ma ta=-40c ta=25c ta=95c ta=125c 1
st6200c st6201c st6203c 80/100 doc id 4563 rev 5 i/o port pin characteristics (cont?d) figure 62. typical v oh vs v dd 3456 vdd [v] 2 3 4 5 6 voh [v] at iio=-2ma ta=-40c ta=25c ta=95c ta=125c 3456 vdd [v] 1 2 3 4 5 6 voh [v] at iio=-5ma ta=-40c ta=25c ta=95c ta=125c 1
st6200c st6201c st6203c doc id 4563 rev 5 81/100 10.9 control pin characteristics 10.9.1 asynchronous reset pin subject to general operat ing conditions for v dd , f osc , and t a unless otherwise specified. notes: 1. unless otherwise specified, typical data are based on t a =25c and v dd =5v. 2. data based on characterization results, not tested in production. 3. hysteresis voltage between schmitt trigger switching le vels. based on characterization results, not tested. 4. the r on pull-up equivalent resistor is based on a resistive transis tor. this data is based on characterization results, not tested in production. 5. all short pulse applied on reset pin with a duration below t h(rstl)in can be ignored. 6. the reset network protects the device against par asitic resets, especially in a noisy environment. 7. the output of the external reset circuit must have an open-drain output to drive the st6 reset pad. otherwise the device can be damaged when the st6 generates an internal reset (lvd or watchdog). figure 63. typical r on vs v dd with v in =v ss symbol parameter conditions min typ 1) max unit v il input low level voltage 2) 0.3xv dd v v ih input high level voltage 2) 0.7xv dd v hys schmitt trigger voltage hysteresis 3) 200 400 mv r on weak pull-up equivalent resistor 4) v in = v ss v dd =5v 150 350 900 k v dd =3.3v 300 730 1900 r esd esd resistor protection v in = v ss v dd =5v 2.8 k v dd =3.3v t w(rstl)out generated reset pulse duration external pin or internal reset sources t cpu s t h(rstl)in external reset pulse hold time 5) s t g(rstl)in filtered glitch duration 6) ns 34 56 vdd [v] 100 200 300 400 500 600 700 800 900 1000 ron [kohm] ta=-40c ta=25c ta=95c ta=125c 1
st6200c st6201c st6203c 82/100 doc id 4563 rev 5 control pin characteristics (cont?d) figure 64. typical application with reset pin 8) 10.9.2 nmi pin subject to general operat ing conditions for v dd , f osc , and t a unless otherwise specified. notes: 1. unless otherwise specified, typical data are based on t a =25c and v dd =5v. 2. data based on characterization results, not tested in production. 3. hysteresis voltage between schmitt trigger switching le vels. based on characterization results, not tested. 4. the r pull-up equivalent resistor is based on a resistive transistor. th is data is based on characterization results, not tested in production. figure 65. typical r pull-up vs. v dd with v in =v ss 0.1 f v dd 0.1 f v dd 4.7k external reset circuit 7) opt i onal f int counter reset watchdog reset lvd reset internal reset r esd 1) v dd r pu stop mode 2048 external clock cycles symbol parameter conditions min typ 1) max unit v il input low level voltage 2) 0.3xv dd v v ih input high level voltage 2) 0.7xv dd v hys schmitt trigger voltage hysteresis 3) 200 400 mv r pull-up weak pull-up equivalent resistor 4) v in = v ss v dd =5v 40 100 350 k v dd =3.3v 80 200 700 34 56 vdd [v] 50 100 150 200 250 300 rpull-up [kohm] ta=-40c ta=25c ta=95c ta=125c 1
st6200c st6201c st6203c doc id 4563 rev 5 83/100 control pin characteristics (cont?d) 10.10 timer peripheral characteristics subject to general oper ating conditions for v dd , f osc , and t a unless otherwise specified. refer to i/o port characteristics for more details on the input/output alternate function characteristics (timer). 10.10.1 watchdog timer 10.10.2 8-bit timer symbol parameter conditions min typ max unit t w(wdg) watchdog time-out duration 3,072 196,608 t int f cpu =4mhz 0.768 49.152 ms f cpu =8mhz 0.384 24.576 ms symbol parameter conditions min typ max unit f ext timer external clock frequency 0 f int /4 mhz t w pulse width at timer pin vdd>4.5v 125 ns vdd=3v 1 s 1
st6200c st6201c st6203c 84/100 doc id 4563 rev 5 10.11 8-bit adc characteristics subject to general operat ing conditions for v dd , f osc , and t a unless otherwise specified. notes: 1. unless otherwise specified, typical data are based on t a =25c and v dd =5v. 2. the adc refers to v dd and v ss . 3. any added external serial resistor will downgrade the adc accuracy (especially for resistance greater than 10k ). data based on characterization results, not tested in production. 4. as a stabilization time for the ad converter is r equired, the first conversion after the enable can be wrong. figure 66. typical application with adc note: adc not present on some devices. see device summary on page 1. symbol parameter conditions min typ 1) max unit f osc clock frequency 1.2 f osc mhz v ain conversion range voltage 2) v ss v dd v r ain external input resistor 10 3) k t adc total convertion time f osc =8mhz f osc =4mhz 70 140 s t stab stabilization time 4) 2 4 t cpu f osc =8mhz 3.25 6.5 s ad i analog input current during conver - sion 1.0 a ac in analog input capacitance 2 5 pf ainx st62xx v ain r ain 10pf adc 10m r 150
st6200c st6201c st6203c doc id 4563 rev 5 85/100 8-bit adc characteristics (cont?d) adc accuracy notes: 1. negative injection disturbs the analog performance of the dev ice. in particular, it induces leakage currents throughout the device including the analog inputs. to avoid undesir able effects on the analog functions, care must be taken: - analog input pins must have a negative injection less than 1ma (assuming that the impedance of the analog voltage is lower than the specified limits). - pure digital pins must have a negative injection less than 1m a. in addition, it is recommended to inject the current as far as possible from the analog input pins. 2. data based on characterization results over th e whole temperature range, monitored in production. figure 67. adc accuracy characteristics note: adc not present on some devices. see device summary on page 1. symbol parameter conditions min typ. max unit |e t | total unadjusted error 1) v dd =5v 2) f osc =8mhz 1.2 2, fosc>1.2mhz 4, fosc>32khz lsb e o offset error 1) 0.72 e g gain error 1) -0.31 |e d | differential linearity error 1) 0.54 |e l | integral linearity error 1) e o e g 1lsb ideal 1lsb ideal v dda v ssa ? 256 ---------------------------------------- - = v in (lsb ideal ) (1) example of an actual transfer curve (2) the ideal transfer curve (3) end point correlation line e t =total unadjusted error: maximum deviation between the actual and the ideal transfer curves. e o =offset error: deviation between the first actual transition and the first ideal one. e g =gain error: deviation between the last ideal transition and the last actual one. e d =differential linearity error: maximum deviation between actual steps and the ideal one. e l =integral linearity error: maximum deviation between any actual transition and the end point correlation line. digital result adcdr 255 254 253 5 4 3 2 1 0 7 6 1234567 253 254 255 256 (1) (2) e t e d e l (3) v dda v ssa 1
st6200c st6201c st6203c 86/100 doc id 4563 rev 5 11 general information 11.1 package mechanical data figure 68. 16-pin plastic dual in-line package, 300-mil width figure 69. 16-pin plastic small outline package, 300-mil width dim. mm inches min typ max min typ max a 5.33 0.210 a1 0.38 0.015 a2 2.92 3.30 4.95 0.115 0.130 0.195 b 0.36 0.46 0.56 0.014 0.018 0.022 b2 1.14 1.52 1.78 0.045 0.060 0.070 b3 0.76 0.99 1.14 0.030 0.039 0.045 c 0.20 0.25 0.36 0.008 0.010 0.014 d 18.67 19.18 19.69 0.735 0.755 0.775 d1 0.13 0.005 e 2.54 0.100 e 7.62 7.87 8.26 0.300 0.310 0.325 e1 6.10 6.35 7.11 0.240 0.250 0.280 l 2.92 3.30 3.81 0.115 0.130 0.150 eb 10.92 0.430 number of pins n 16 c e e1 eb l a a2 a1 e b b2 b3 d1 d dim. mm inches min typ max min typ max a 2.35 2.65 0.093 0.104 a1 0.10 0.30 0.004 0.012 b 0.33 0.51 0.013 0.020 c 0.23 0.32 0.009 0.013 d 10.10 10.50 0.398 0.413 e 7.40 7.60 0.291 0.299 h 10.00 10.65 0.394 0.419 e 1.27 0.050 h 0.25 0.75 0.010 0.030 0 8 0 8 l 0.40 1.27 0.016 0.050 number of pins n 16 h e c h x 45 a l b e a1 a d 1
st6200c st6201c st6203c doc id 4563 rev 5 87/100 package mechanical data (cont?d) figure 70. 16-pin ceramic side-brazed dual in-line package figure 71. 16-pin plastic shrink small outline package dim. mm inches min typ max min typ max a 3.78 0.149 a1 0.38 0.015 b 0.36 0.46 0.56 0.014 0.018 0.022 b1 1.14 1.37 1.78 0.045 0.054 0.070 c 0.20 0.25 0.36 0.008 0.010 0.014 d 19.86 20.32 20.78 0.782 0.800 0.818 d1 17.78 0.700 e1 7.04 7.49 7.95 0.277 0.295 0.313 e 2.54 0.100 g 6.35 6.60 6.86 0.250 0.260 0.270 g1 9.47 9.73 9.98 0.373 0.383 0.393 g2 1.02 0.040 l 2.92 3.30 3.81 0.115 0.130 0.150 s 1.27 0.050 ? 4.22 0.166 number of pins n16 cdip16w dim. mm inches min typ max min typ max a 2.00 0.079 a1 0.05 0.002 a2 1.65 1.75 1.85 0.065 0.069 0.073 b 0.22 0.38 0.009 0.015 c 0.09 0.25 0.004 0.010 d 5.90 6.20 6.50 0.232 0.244 0.256 e 7.40 7.80 8.20 0.291 0.307 0.323 e1 5.00 5.30 5.60 0.197 0.209 0.220 e 0.65 0.026 0 4 8 0 4 8 l 0.55 0.75 0.95 0.022 0.030 0.037 number of pins n 16 a2 a1 a d b e e1 e l h c 1
st6200c st6201c st6203c 88/100 doc id 4563 rev 5 11.2 thermal characteristics notes: 1. the power dissipation is obtained from the formula p d = p int + p port where p int is the chip internal power (i dd xv dd ) and p port is the port power dissipation determined by the user. 2. the average chip-junction temperature can be obtained from the formula t j = t a + p d x rthja. symbol ratings value unit r thja package thermal resistance (junction to ambient) dip16 so16 ssop16 90 90 125 c/w p d power dissipation 1) 500 mw t jmax maximum junction temperature 2) 150 c 1
st6200c st6201c st6203c doc id 4563 rev 5 89/100 11.3 ecopack information in order to meet environmental requirements, st offers these devices in different grades of eco - pack ? packages, depending on their level of en - vironmental compliance. ecopack ? specifica - tions, grade definitions and product status are available at: www.st.com. ecopack ? is an st trademark. 1
st6200c st6201c st6203c 90/100 doc id 4563 rev 5 11.4 package/socket footprint proposal table 21. suggested list of dip16 socket types table 22. suggested list of so16 socket types table 23. suggested list of ssop16 socket types package / probe adaptor / socket reference same footprint socket type dip16 textool 216-33-40 x textool package / probe adaptor / socket reference same footprint socket type so16 enplas ots-16-1.27-04 open top yamaichi ic51-347.ks-7704 clamshell emu probe adapter from so16 to dip16 footprint (delivered with emulator) x smd to dip programming adapter logical systems pa16so1-08h-6 x open top package / probe adaptor / socket reference same footprint socket type ssop16 enplas ots-16-0.65-01 open top emu probe adapter from ssop16 to dip16 footprint (sales type: st626x-p/ssop16) x smd to dip programming adapter logical systems pa16ss-ot-6 x open top 1
st6200c st6201c st6203c doc id 4563 rev 5 91/100 11.5 ordering information the following section deals with the procedure for transfer of customer c odes to stmicroelectronics and also details the st6 factory coded device type. for a list of available options (e.g. memory size, package) and orderable part numbers or for fur - ther information on any aspect of this device, please go to www.st.com or contact the st sales office nearest to you. figure 72. st6 factory coded device types rom code temperature code: 1: standard 0 to +70 c 3: automotive -40 to +125 c 6: industrial -40 to +85 c package type: b: plastic dip d: ceramic dip (only for eeprom) m: plastic sop n: plastic ssop t: plastic tqfp revision index: b,c: product definition change l: low voltage device st6 sub family version code: no char: rom e: eprom p: fastrom t: otp family ST62T03CB6/ccc 1
st6200c st6201c st6203c 92/100 doc id 4563 rev 5 11.6 transfer of customer code customer code is made up of the rom contents and the list of the selected fastrom options. the rom contents are to be sent on diskette, or by electronic means, with the hexadecimal file generated by the development tool. all unused bytes must be set to ffh. the selected options are communicated to stmicroelectronics using the correctly filled op - tion list appended. see page 94 . the stmicroelectronics sa les organization will be pleased to provide detailed information on con - tractual points. listing generation and verification. when stmicroelectronics receiv es the user?s rom con - tents, a computer listing is generated from it. this listing refers exactly to the rom contents and op - tions which will be used to produce the specified mcu. the listing is then returned to the customer who must thoroughly check, complete, sign and return it to stmicroelec tronics. the signed listing forms a part of the contractual agreement for the production of the specific customer mcu. 11.6.1 fastrom version the st62p00c, p01c and p03c are the f actory a dvanced s ervice t echnique rom (fastrom) versions of st62t00c, t01 and t03c otp devic - es. they offer the same functionality as otp devices, but they do not have to be programmed by the customer. the customer code must be sent to stmicroelectronics in the same way as for rom devices. the fastrom option list has the same options as defined in the programmable option byte of the otp version. it also offers an identifier option. if this option is enabled, each fastrom device is programmed with a unique 5-byte number which is mapped at addresses 0f9bh- 0f9fh. the user must therefore leave these bytes blanked. the identification number is structured as follows: with t0, t1, t2, t3 = time in seconds since 01/01/ 1970 and test id = tester identifier. 0f9bh t0 0f9ch t1 0f9dh t2 0f9eh t3 0f9fh test id 1
st6200c st6201c st6203c doc id 4563 rev 5 93/100 transfer of customer code (cont?d) 11.6.2 rom version the st6200c, 01c and 03c are mask pro - grammed rom version of st62t00c, t01 and t03c otp devices. they offer the same functionality as otp devices, selecting as rom options the options defined in the programmable option byte of the otp version. figure 73. programming circuit note: zpd15 is used for overvoltage protection rom readout protection. if the rom readout protection option is selected, a protection fuse can be blown to prevent any access to the program memory content. in case the user wants to blow this fuse, high volt - age must be applied on the v pp pin. figure 74. programming wave form vr02003 v pp 5v 100nf 4.7f protect 100nf v dd v ss zpd15 15v 14v 100 s max 0.5s min v pp 15 14v typ 10 5 v pp 400ma 4ma typ vr02001 max 150 s typ t 1
st6200c st6201c st6203c 94/100 doc id 4563 rev 5 transfer of customer code (cont?d) st6200c/01c/03c/p00c/p01c/p03c microcontroller option list customer: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . address: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . contact: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . phone: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . reference: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . stmicroelectronics references: device: [ ] st6200c (1 kb) [ ] st62p00c (1 kb) [ ] st6201c (2 kb) [ ] st62p01c (2 kb) [ ] st6203c (1 kb) [ ] st62p03c (1 kb) package: [ ] dual in line plastic [ ] small outline plastic with conditioning [ ] shrink small outline plastic with conditioning conditioning option: [ ] standard (tube) [ ] tape & reel temperature range: [ ] 0c to + 70c [ ] - 40c to + 85c [ ] - 40c to + 125c marking: [ ] standard marking [ ] special marking (rom only): pdip16 (9 char. max): _ _ _ _ _ _ _ _ _ so16 (6 char. max): _ _ _ _ _ _ ssop16 (10 char. max): _ _ _ _ _ _ _ _ _ _ authorized characters are letters, di gits, '.', '-', '/' and spaces only. oscillator safeguard: [ ] enabled [ ] disabled watchdog selection: [ ] software activation [ ] hardware activation nmi pull-up: [ ] enabled [ ] disabled oscillator selection: [ ] quartz crystal / ceramic resonator [ ] rc network readout protection: fastrom: [ ] enabled [ ] disabled rom: [ ] enabled: [ ] fuse is blown by stmicroelectronics [ ] fuse can be blown by the customer [ ] disabled low voltage detector: [ ] enabled [ ] disabled external stop mode control: [ ] enabled [ ] disabled identifier (fastrom only): [ ] enabled [ ] disabled comments: oscillator frequency in the application: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . supply operating range in the application: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . notes: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . date: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . signature: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
st6200c st6201c st6203c doc id 4563 rev 5 95/100 12 development tools stmicroelectronics offers a range of hardware and software development tools for the st6 micro - controller family. full detai ls of tools available for the st6 from third party manufacturers can be ob - tain from the stmicroelectronics internet site: ? http://www.st.com. table 24. dedicated third parties development tools note 1: for latest information on third party tools, please visit our internet site: ? http://www.st.com. third party 1) designation st sales type web site address actum st-realizer ii: graphical schematic based development available from stmicroelectronics. strealizer-ii http://www.actum.com/ ceibo low cost emulator available from cei - bo. http://www.ceibo.com/ raisonance this tool includes in the same environ - ment: an assembler, linker, c compiler, debugger and simulator. the assembler package (plus limited c compiler) is free and can be downloaded from raisonance web site. the full version is available both from stmicroelectronics and raiso - nance. st6rais-swc/ pc http://www.raisonance.com/ softec high end emulator available from softec. http://www.softecmicro.com/ gang programmer available from softec. advanced equipment single and gang programmers http://www.aec.com.tw/ advanced transdata http://www.adv-transdata.com/ bp microsystems http://www.bpmicro.com/ data i/o http://www.data-io.com/ dataman http://www.dataman.com/ ee tools http://www.eetools.com/ elnec http://www.elnec.com/ hi-lo systems http://www.hilosystems.com.tw/ ice technology http://www.icetech.com/ leap http://www.leap.com.tw/ lloyd research http://www.lloyd-research.com/ logical devices http://www.chipprogram - mers.com/ mqp electronics http://www.mqp.com/ needhams electronics http://www.needhams.com/ stag programmers http://www.stag.co.uk/ system general corp http://www.sg.com.tw tribal microsystems http://www.tribalmicro.com/ xeltek http://www.xeltek.com/ 1
st6200c st6201c st6203c 96/100 doc id 4563 rev 5 development tools (cont?d) stmicroelectronics tools four types of development tool are offered by st, all of them connect to a pc via a parallel or serial port: see table 25 and table 26 for more details. table 25. stmicroelectronics tool features table 26. dedicated stmicroelectronics development tools emulation type programming capability software included st6 starter kit device simulation (limited emulation as interrupts are not supported) yes (dip packages only) mcu cd rom with: ? rkit-st6 from raisonance ? st6 assembly toolchain ? wgdb6 powerful source level debugger for win 3.1, win 95 and nt ? various software demo ver - sions. ? windows programming tools for win 3.1, win 95 and nt st6 hds2 emulator in-circuit powerful emula - tion features including trace/ logic analyzer no st6 eprom programmer board no yes (all packages except ssop) supported products st6 starter kit st6 hds2 emulator st6 programming board st6200c, 001c and 003c st622xc-kit complete: st62gp-emu2 dedication board: st62gp-dbe st62e2xc-epb 1
st6200c st6201c st6203c doc id 4563 rev 5 97/100 13 st6 application notes identification description motor control an392 microcontroller and triacs on the 110/240v mains an414 controlling a brush dc motor with an st6265 mcu an416 sensorless motor drive with the st62 mcu + triac an422 improves universal motor drive an863 improved sensorless control with the st62 mcu for universal motor battery management an417 from nicd to nimh fa st battery charging an433 ultra fast battery charger using st6210 microcontroller an859 an intelligent one hour multicharger for li-ion, nimh and nicd batteries home appliance an674 microcontrollers in home appliances: a soft revolution an885 st62 microcontrollers drive ho me appliance motor technology graphical design an676 battery charger using the st6-realizer an677 painless microcontroller code by graphical application description an839 analog multiple key decoding using the st6-realizer an840 coded lock using the st6-realizer an841 a clock design using the st6-realizer an842 7 segment display drive using the st6-realizer cost reduction an431 using st6 analog inputs for multiple key decoding an594 direct software lcd drive with st621x and st626x an672 optimizing the st6 a/d converter accuracy an673 reducing current consumpt ion at 32khz with st62 design improvements an420 expanding a/d resolution of the st6 a/d converter an432 using st62xx i/o ports safely an434 movement detector concept s for noisy environments an435 designing with microcontrollers in noisy environments an669 simple reset circuits for the st6 an670 oscillator selection for st62 an671 prevention of data corruption in st6 on-chip eeprom an911 st6 micro is emc champion an975 upgrading from st625x/6xb to st625x/6xc an1015 software techniques for improving st6 emc performance peripheral operations an590 pwm generation with st62 auto-reload timer an591 input capture with st62 auto-reload timer an592 pll generation using the st62 auto-reload timer an593 st62 in-circuit programming an678 lcd driving with st6240 1
st6200c st6201c st6203c 98/100 doc id 4563 rev 5 an913 pwm generation with st62 16-bit auto-reload timer an914 using st626x spi as uart an1016 st6 using the st623xb/st628xb uart an1050 st6 input capture with st62 16-bit auto-reload timer an1127 using the st62t6xc/5xc spi in master mode general an683 mcus - 8/16-bit microcontrollers (m cus) application notes abstracts by topics an886 selecting between rom and otp for a microcontroller an887 making it easy with microcontrollers an898 emc general information an899 soldering recommendations a nd packaging information an900 introduction to semiconductor technology an901 emc guide-lines for microcontroller - based applications an902 quality and reliability information an912 a simple guide to development tools an1181 electrostatic disharge sensitivity measurement identification description 1
st6200c st6201c st6203c doc id 4563 rev 5 99/100 14 summary of changes description of the changes between the current releas e of the specification and the previous one. 15 to get more information to get the latest information on this produc t please use the stmicr oelectronics web server. ? http://www.st.com/ revision main changes date 3.3 removed references to 32768 clock cycle delay in section 5 and in section 6 changed note 2 in section 10.6.2 on page 72 : added text on data retention and program - mability. october 2003 4 updated device summary on page 1 replaced soldering information by ecopack ? information in section 11.3 on page 89 updated disclaimer on last page january 2009 5 added note 5 to section 10.2.2 on page 59 october 2009 1
st6200c st6201c st6203c 100/100 doc id 4563 rev 5 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modi fications or improvements, to this docume nt, and the products and services describe d herein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any expre ss or implied war - ranty with respect to the use and/or sale of st pro ducts including without limi tation implied warranties of merchantability, fitness for a particular purpose (and their equivalents under the laws of any juris - diction), or infringement of any patent, co pyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recom - mended, authorized or warranted for use in military, air craft, space, life saving, or life sustaining appli - cations, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statemen ts and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner wha tsoever, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2009 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com 1

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